-0- ML-RSIM Reference Manual Lambert Schaelicke Department of Computer Science and Engineering University of Notre Dame Mike Parker School of Computing University of Utah University of Notre Dame Department of Computer Science and Engineering Technical Report 02-10 November/02 CONTENTS Part I: Simulator Overview 1 Introduction. 1 2 System Architecture . 2 2.1 System Architecture Configuration . 3 2.2 Address Map . 3 2.3 Simulator Page Table. 4 3 Parameter Setup . 5 4 Simulation Input/Output Files . 6 5 Multiprocessor Simulation . 7 6 Kernel Image. 8 7 File Descriptor Management. 9 8 User Statistics . 10 8.1 User Statistics Management. 10 8.2 User Statistics Structures . 10 Part II: Processor Model 1 Overview. 11 2 Fundamental Data Structures . 13 2.1 Dynamic Instructions. 13 2.2 Activelist . 13 2.3 Stall Queues . 13 2.4 Heaps . 14 2.5 Processor State. 14 3 Parameters. 15 4 Register File . 17 4.1 Register Definition. 19 4.2 Register Access . 20 5 Little Endian Host Support . 21 6 Instruction Fetch Stage . 22 7 Instruction Decode Stage . 24 7.1 Instruction Decode. 24 7.2 Dependency Checking . 24 -ii- 7.3 Context Synchronization . 25 8 Instruction Issue and Completion . 26 8.1 Issue . 26 8.2 Completion. 26 9 Instruction Graduation Stage . 27 10 Memory Instruction . 28 10.1 Memory Instruction Issue . 28 10.2 Memory Instruction Completion . 28 10.3 Memory Disambiguation . 29 10.4 Address Generation . 30 10.5 Uncached Load/Store Instructions. 30 10.6 Memory Barrier & Uncached Buffer. 30 11 Exception & Interrupt Handling . 31 11.1 Trap Table . 32 11.2 Exception Detection. 32 11.3 Exception Handling . 32 11.4 System Call Traps . 33 11.5 External Interrupts . 33 11.6 Statistics . 34 12 System Calls and Simulator Traps . 35 12.1 System Call Interface. 35 12.2 Simulator Trap Handling . 35 12.3 Simulator OS Bootstrap Information. 35 12.4 File I/O Simulator Traps . 36 12.5 Socket Simulator Traps . 38 12.6 Statistics Simulator Traps . 38 12.7 Miscellaneous Simulator Traps . 39 13 Instruction & Data TLB . 40 13.1 TLB Configuration. 40 13.2 TLB Entry Format . 41 13.3 TLB WriteEntry. 42 13.4 TLB LookUp . 42 13.5 TLB Probe and Flush. 43 Part III: Memory Hierarchy 1 Overview. ..