Glossary G-1 Glossary absolute address A variable’s or routine’s Amdahl’s law A rule stating that the per- actual address in memory. formance enhancement possible with a giv- abstraction A model that renders lower- en improvement is limited by the amount level details of computer systems tempo- that the improved feature is used. rarily invisible in order to facilitate design of antidependence Also called name depen- sophisticated systems. dence. An ordering forced by the reuse of a acronym A word constructed by taking the name, typically a register, rather then by a initial letters of string of words. For exam- true dependence that carries a value be- ple: RAM is an acronym for Random Access tween two instructions. Memory, and CPU is an acronym for Cen- antifuse A structure in an integrated cir- tral Processing Unit. cuit that when programmed makes a per- active matrix display A liquid crystal dis- manent connection between two wires. play using a transistor to control the trans- application binary interface (ABI) The mission of light at each individual pixel. user portion of the instruction set plus address translation Also called address the operating system interfaces used by mapping. The process by which a virtual ad- application programmers. Defines a dress is mapped to an address used to access standard for binary portability across memory. computers. address A value used to delineate the loca- architectural registers The instruction set tion of a specific data element within a visible registers of a processor; for example, memory array. in MIPS, these are the 32 integer and 16 addressing mode One of several address- floating-point registers. ing regimes delimited by their varied use of arithmetic mean The average of the execu- operands and/or addresses. tion times that is directly proportional to advanced load In IA-64, a speculative load total execution time. instruction with support to check for aliases assembler directive An operation that tells that could invalidate the load. the assembler how to translate a program aliasing A situation in which the same ob- but does not produce machine instructions; ject is accessed by two addresses; can occur always begins with a period. in virtual memory when there are two virtu- assembler A program that translates a al addresses for the same physical page. symbolic version of instructions into the bi- alignment restriction A requirement that nary version. data be aligned in memory on natural assembly language A symbolic language boundaries that can be translated into binary. G-2 Glossary asserted signal A signal that is (logically) bit error rate The fraction in bits of a true, or 1. message or collection of messages that is asynchronous bus A bus that uses a hand- incorrect. shaking protocol for coordinating usage block The minimum unit of information rather than a clock; can accommodate a that can be either present or not present in wide variety of devices of differing speeds. the two-level hierarchy. atomic swap operation An operation in blocking assignment In Verilog, an assign- which the processor can both read a loca- ment that completes before the execution of tion and write it in the same bus operation, the next statement. preventing any other processor or I/O branch delay slot The slot directly after a device from reading or writing memory un- delayed branch instruction, which in the til it completes. MIPS architecture is filled by an instruction backpatching A method for translating that does not affect the branch. from assembly language to machine in- branch not taken A branch where the structions in which the assembler builds a branch condition is false and the program (possibly incomplete) binary representation counter (PC) becomes the address of the in- of every instruction in one pass over a pro- struction that sequentially follows the gram and then returns to fill in previously branch. undefined labels. branch prediction A method of resolving a backplane bus A bus that is designed to al- branch hazard that assumes a given out- low processors, memory, and I/O devices to come for the branch and proceeds from that coexist on a single bus. assumption rather than waiting to ascertain barrier synchronization A synchroniza- the actual outcome. tion scheme in which processors wait at the branch prediction buffer Also called barrier and do not proceed until every pro- branch history table. A small memory that cessor has reached it. is indexed by the lower portion of the ad- basic block A sequence of instructions dress of the branch instruction and that without branches (except possibly at the contains one or more bits indicating wheth- end) and without branch targets or er the branch was recently taken or not. branch labels (except possibly at the branch taken A branch where the branch beginning). condition is satisfied and the program behavioral specification Describes how a counter (PC) becomes the branch target. All digital system operates functionally. unconditional branches are taken branches. biased notation A notation that represents branch target address The address speci- the most negative value by 00 . 000two and fied in a branch, which becomes the new the most positive value by 11 . 11two, with program counter (PC) if the branch is tak- 0 typically having the value 10 . 00two, en. In the MIPS architecture the branch tar- thereby biasing the number such that the get is given by the sum of the offset field of number plus the bias has a nonnegative the instruction and the address of the in- representation. struction following the branch. binary digit Also called a bit. One of the branch target buffer A structure that cach- two numbers in base 2 (0 or 1) that are the es the destination PC or destination instruc- components of information. tion for a branch. It is usually organized as a Glossary G-3 cache with tags, making it more costly than cathode ray tube (CRT) display A display, a simple prediction buffer. such as a television set, that displays an im- bus In logic design, a collection of data age using an electron beam scanned across a lines that is treated together as a single logi- screen. cal signal; also, a shared collection of lines central processor unit (CPU) Also called with multiple sources and uses. processor. The active part of the computer, bus master A unit on the bus that can ini- which contains the datapath and control tiate bus requests. and which adds numbers, tests numbers, bus transaction A sequence of bus opera- signals I/O devices to activate, and so on. tions that includes a request and may in- clock cycle Also called tick, clock tick, clude a response, either of which may carry clock period, clock, cycle. The time for one data. A transaction is initiated by a single re- clock period, usually of the processor clock, quest and may take many individual bus op- which runs at a constant rate. erations. clock cycles per instruction (CPI) Average cache coherency Consistency in the value number of clock cycles per instruction for a of data between the versions in the caches of program or program fragment. several processors. clock period The length of each clock cycle. cache coherent NUMACC-NUMA A non- clock skew The difference in absolute time uniform memory access multiprocessor between the times when two state elements that maintains coherence for all caches. see a clock edge. cache memory A small, fast memory that clocking methodology The approach used acts as a buffer for a slower, larger memory. to determine when data is valid and stable cache miss A request for data from the relative to the clock. cache that cannot be filled because the data cluster A set of computers connected over is not present in the cache. a local area network (LAN) that function as callee A procedure that executes a series of a single large multiprocessor. stored instructions based on parameters combinational logic A logic system whose provided by the caller and then returns con- blocks do not contain memory and hence trol to the caller. compute the same output given the same callee-saved register A register saved by input. the routine making a procedure call. commit unit The unit in a dynamic or out- caller The program that instigates a proce- of-order execution pipeline that decides dure and provides the necessary parameter when it is safe to release the result of an op- values. eration to programmer-visible registers and caller-saved register A register saved by memory. the routine being called. compiler A program that translates high- capacity miss A cache miss that occurs be- level language statements into assembly cause the cache, even with full associativity, language statements. cannot contain all the block needed to satis- compulsory miss Also called cold start fy the request. miss. A cache miss caused by the first access carrier signal A continuous signal of a sin- to a block that has never been in the cache. gle frequency capable of being modulated conditional branch An instruction that re- by a second data-carrying signal. quires the comparison of two values and G-4 Glossary that allows for a subsequent transfer of con- D flip-flop A flip-flop with one data input trol to a new address in the program based that stores the value of that input signal in on the outcome of the comparison. the internal memory when the clock edge conflict miss Also called collision miss. A occurs. cache miss that occurs in a set-associative or data hazard Also called pipeline data haz- direct-mapped cache when multiple blocks ard.