UnitUnit 3.5.3.5. HardwareHardware descriptiondescription languageslanguages Digital Electronic Circuits E.T.S.I. Informática Universidad de Sevilla Jorge Juan-Chico <[email protected]> 2010-2020 This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA. Departamento de Tecnología Electrónica – Universidad de Sevilla 1 ContenidosContenidos ● Lenguajes de descripción de hardware ● Tipos de descripciones ● Estructura de una descripción Verilog ● Verilog: sintaxis y estructuras principales ● Banco de pruebas y simulación ● Síntesis desde LDH en FPGA ● Herramientas de diseño básicas Departamento de Tecnología Electrónica – Universidad de Sevilla 2 BibliographyBibliography ● Recommended: – LaMeres book: ● 5.1, 5.2, 5.3: introduction to hardware description languages and to the modern digital design flow. – Verilog course based on examples [web] ● Unit 1: introduction. ● Unit 2: test benches. ● Unit 3: combinational circuits ● Verilog reference (use when coding in Verilog) – Verilog HDL Quick Reference Guide (Verilog-2001 standard) – LaMeres 5.4 to 5.7: Verilog language, functional and structural descriptions and logic primitives. Departamento de Tecnología Electrónica – Universidad de Sevilla 3 WhatWhat isis aa hardwarehardware descriptiondescription language?language? ● Formal language used to describe the behavior of an (digital) electronic circuit. ● Similar to a programming language but with notable differences: – Most statements “execute” concurrently – Every statement is translated to a circuit block //// ANDAND operationoperation xx == aa && b;b; //// OROR operationoperation yy == aa || b;b; //// CombinationalCombinational functionfunction zz == xy'xy' ++ x'yx'y zz == xx && ~y~y || ~x~x && y;y; Departamento de Tecnología Electrónica – Universidad de Sevilla 4 WhyWhy areare HDL'sHDL's useful?useful? ● Simulación – Using a circuit description, a software tool (simulator) can check how the circuit will operate before building the real circuit. ● Automatic synthesis – Automatic circuit implementation using software tools – Equivalent to software's “compilation” – Makes digital design really simple and productive – Be careful! The designer should know what the tool can and cannot do. Departamento de Tecnología Electrónica – Universidad de Sevilla 5 VHDLVHDL vsvs VerilogVerilog ● VHDL ● Verilog – More complex syntax (ADA- – More simple syntax (C-like) like) – Easier to learn (I think...) – More strict syntax (reduce – Language versions errors) ● Verilog – Better support for big designs – 1995, 2001, 2005 ● System Verilog – 2005, 2009, 2012, 2017, ... Both VHDL and Verilog are well supported by hardware vendors and can be used interchangeably even in the same project. It is mostly a matter of personal taste. Departamento de Tecnología Electrónica – Universidad de Sevilla 6 Example:Example: votervoter circuitcircuit ● Logic expression a – z = ab+ac+bc b voter z ● c Verilog expression – z = a&b | a&c | b&c; a b c z 0 0 0 0 0 0 1 0 modulemodule voter(voter( 0 1 0 0 outputoutput z,z, inputinput a,a, 0 1 1 1 inputinput b,b, inputinput cc 1 0 0 0 );); 1 0 1 1 assignassign zz == a&ba&b || a&ca&c || b&c;b&c; 1 1 0 1 endmoduleendmodule 1 1 1 1 Departamento de Tecnología Electrónica – Universidad de Sevilla 7 TypesTypes ofof descriptionsdescriptions assign z = a&b | a&c | b&c; ● Functional (continuous assignment) always @(a, b, c) – Models combinational logic by using if (a == 1) assignment of an expression. if (b == 1 || c == 1) z = 1; ● else Procedural (always block) z = 0; – else Allow control structures if (b == 1 && c == 1) – z = 1; Algorithmic description similar to else software z = 0; – Easier to express complex functions a and1 out1 b ● Structural out3 and3 or1 z c – Connection of circuit modules and2 out2 – Equivalent to a circuit schematic wire out1, out2, out3; – Verilog includes logic gates as built-in modules and and1 (out1, a, b); and and2 (out2, b, c); and and3 (out3, a, c); or or1 (z, out1, out2, out3); Departamento de Tecnología Electrónica – Universidad de Sevilla 8 VerilogVerilog descriptiondescription structurestructure `timescale 1ns / 1ps ● Pre-processor directives ● // Module: cvoter Module declaration // Conditional voting circuit – Module name // z = ab + bc + ac if x=1 // if no, z = 0; – Input and output ports module cvoter( ● Signal declaration input wire x, input wire a, – Name and type of internal signals input wire b, input wire c, ● Design description output reg z – Processing structures ); – Expressions wire v; – … assign v = a&b | b&c | a&c; ● Any number of modules can be described always @(*) in a single file if (x == 1) z = v; ● Comments else z = 0; – //, /* … */ endmodule // cvoter Departamento de Tecnología Electrónica – Universidad de Sevilla 9 VerilogVerilog syntaxsyntax Your need a language reference if you are coding in Verilog. This is a good one. Verilog HDL Quick Reference Guide by Stuart Sutherland http://sutherland-hdl.com/pdfs/verilog_2001_ref_guide.pdf Departamento de Tecnología Electrónica – Universidad de Sevilla 10 Verilog:Verilog: portsports andand signalssignals `timescale 1ns / 1ps ● Basic signal types // Module: cvoter – wire: a permanent connection. Used // Conditional voting circuit for modules connections and “assign”. // z = ab + bc + ac if x=1 // if no, z = 0; – reg: a variable that can be assigned module cvoter( multiple times. Used in procedures input wire x, like “always”. input wire a, input wire b, ● An internal signal is automatically input wire c, output reg z created for every input/output port ); (with the same name) wire v; ● Signal type can be declared with the assign v = a&b | b&c | a&c; port list or in the body of the module. always @(*) By default, signals are of type "wire". if (x == 1) z = v; else z = 0; endmodule // cvoter Departamento de Tecnología Electrónica – Universidad de Sevilla 11 Verilog:Verilog: continuouscontinuous assignmentsassignments ● Circuit behavior description by using an expression. ● Direct way to describe a logic function if the logic expression is already known. ● Many operators can be used in expressions: logic, arithmetic, etc. ● Continuous assignments can only assign “wire” type signals. ... wire v; wire z; assign v = a&b | b&c | a&c; assign z = (x == 1) ? v : 0; ... Departamento de Tecnología Electrónica – Universidad de Sevilla 12 Verilog:Verilog: proceduralprocedural blocksblocks ● Circuit behavior description by using control structures: if, case, for, etc. ● Similar to software, but the circuit doesn't “execute” a procedure at all. ● Only variables (type reg) can be assigned in a procedure. ● Main types of procedures in Verilog: – initial ● Dvaluated only once during simulation. ● Mainly useful in test benches (we'll see later). – always ● Constantly evaluated during simulation. ● A “sensitivity list” may control when the procedure's evaluation starts. Departamento de Tecnología Electrónica – Universidad de Sevilla 13 Verilog:Verilog: concurrencyconcurrency ● All these structures are evaluated (during simulation) concurrently: the order in which they are placed in the Verilog source file does not matter. – Continuous assignments. – Procedural blocks. – Module's instances. ... ... assign v = a&b | b&c | a&c; always @(*) if (x == 1) always @(*) z = v; if (x == 1) else z = v; z = 0; else z = 0; assign v = a&b | b&c | a&c; ... ... Departamento de Tecnología Electrónica – Universidad de Sevilla 14 DesignDesign processprocess usingusing Computer-AidedComputer-Aided DesignDesign (CAD)(CAD) toolstools Word description of the problem Translation LDH description Test bench Simulation Application Specific Integrated Circuit (ASIC) no yes ok? Automatic synthesis Circuit Configurable Circuit Configuration (e.g. FPGA) Departamento de Tecnología Electrónica – Universidad de Sevilla 15 TestTest benchbench andand simulationsimulation ● A test bench is a module that contains: – A circuit to be simulated: Unit Under Test (UUT) – Verilog statements that generate the input signals to the UUT – Verilog simulator directives that control the simulation: time resolution, result printing, simulation ending, etc. ● Test bench characteristics – A TB is not intended to be implemented, only to be simulated. – A TB includes Verilog structures than are only useful for simulation (are not part of the circuit description). – A TB module has no inputs or outputs. Departamento de Tecnología Electrónica – Universidad de Sevilla 16 TestTest benchbench andand simulationsimulation test a signal generation statements Waveform generation b UUT z Results saving Results printing signal generation c statements Configuration Simulation control Departamento de Tecnología Electrónica – Universidad de Sevilla 17 FPGAFPGA ● FPGA – Field Programmable Gate Array – Array of configurable logic devices and connections. ● Configurable Logic Block (CLB) – Can be configured to make any logic operation: AND, OR, XOR, etc. ● Input-Output Block (IOB) – Can be configured as input or output terminals and connected to internal signals. ● Interconnections – Can be configured to interconnect CLB's and IOB's at will. https://en.wikipedia.org/wiki/Field_Programmable_Gate_Array Departamento de Tecnología Electrónica – Universidad de Sevilla 18 FPGAFPGA Xilinx XC4010-6 http://commons.wikimedia.org/wiki/File:Fpga1a.gif Xilinx XC4010-6. Dominio Público https://www.flickr.com/photos/34923408@N07/22054207552/