Model to code generation of UML/SysML activity diagrams for ARM CortexM MCUs MohammadHossein AskariHemmat A Thesis in The Department of Electrical and Computer Engineering Presented in Partial Fulfillment of the Requirements for the Degree of Master Of Applied Science at Concordia University Montreal,´ Quebec,´ Canada April 2015 c MohammadHossein AskariHemmat, 2015 CONCORDIA UNIVERSITY School of Graduate Studies This is to certify that the thesis prepared By: MohammadHossein AskariHemmat Entitled: Model to code generation of UML/SysML activity diagrams for ARM CortexM MCUs and submitted in partial fulfilment of the requirements for the degree of Master of Applied Science (Electrical & Computer Engineering) complies with the regulations of this University and meets the accepted standards with respect to originality and quality. Signed by the final examining committee: Dr. Zahangir Kabir Chair Chair’s name Dr. Samar Abdi Examiner Examiner’s name Dr. Mohammad Mannan Examiner Examiner’s name Dr. Mounir Boukadoum Co-Supervisor Co-Supervisor’s name Dr. Otmane Ait Mohamed Supervisor Supervisor’s name Approved by Chair of the ECE Department 2015 Dean of Engineering ABSTRACT Model to code generation of UML/SysML activity diagrams for ARM CortexM MCUs MohammadHossein AskariHemmat The complexity in embedded systems has been increased in the last years. To over- come the system complexity various methodologies have been presented. Both in industry and academia, Model-Based design has been accepted to be the best solution to solve this problem. Model-Based Design is a technique for developing embedded system applications and cyber-physical systems based on a hierarchy of reusable design blocks. SysML/UML activ- ity diagrams are widely used for the modelling and analysis of complex systems, and they have become the de facto standard for software and embedded systems. Previously in our group, we formalized SysML activity diagrams by developing a calculus called New Activity Calculus (NuAC). In this work, we redefined NuAC terms to support RTX (Keil Real-Time Operating System) and present an automated SysML/UML activity diagram to RTX code generator, using mapping rules expressed in NuAC. To achieve this goal, we proposed a set of mapping rules that were used in mapping a SysM- L/UML activity diagram into a suitable code to be executed on ARM CortexM processor family. To automate the process of code generation, we presented a JAVA application that uses the proposed rules to automatically generate the RTX code from the input activity di- agram model. To demonstrate the capability of the developed tool, we use it to implement a train con- trol algorithm on an ARM Cortex-M4 device. The implemented model is run on the target platform and the correct functionality of the system is verified. iii To my loving family iv ACKNOWLEDGEMENTS First and foremost, I would like to thank the almighty ALLAH for his blessing to finish this research. I would like to express my deepest gratitude to my supervisor, Dr. Otmane Ait Mohamed, for his excellent guidance, caring, patience, and providing me with an excellent atmosphere for doing research. This thesis would not have been possible without his guidance and sup- port. I also want to thank Dr. Mounir Boukadoum, for co-supervising my research work and for giving his valuable comments on my research. I would like to thank all my fellow researchers and colleagues in Hardware Verification Group (HVG) at Concordia University. Without their guidance, support and continual en- couragements, this thesis would not have been possible. I would like to take this opportunity to thank Regroupement Stratgique en Microsystmes du Qubec (ReSMiQ) for their financial supports. Without their financial supports I would not have been able to continue my research work. Last but not least, I thank my family for their constant moral support and their prayers. They are the people who are closest to me and suffered most for my higher study in abroad. Their support was invaluable in completing this thesis. v TABLE OF CONTENTS LIST OF TABLES . viii LIST OF FIGURES . ix LIST OF ACRONYMS . xi 1 Introduction 1 1.1 Motivation . 1 1.2 Related Works . 2 1.2.1 MATLAB and Simulink based modeling . 2 1.2.2 Modeling based on AutoFocus3 . 3 1.2.3 Modeling and Analysis of Real Time and Embedded systems . 4 1.2.4 A Formal Verification Framework for BlueSpec System Verilog . 6 1.3 Proposed Methodology . 7 1.4 Thesis Contribution . 8 1.5 Thesis Outline . 9 2 Preliminaries 11 2.1 SysML and UML modeling languages . 11 2.1.1 Unified Modeling Language . 11 2.1.2 System Modeling Language . 13 2.1.3 Activity Diagrams . 15 2.1.4 SysML/UML based Modeling tools . 18 IBM Rational Rhapsody . 18 Enterprise Architecture . 19 Topcased . 19 2.2 Keil RTX RTOS . 20 2.2.1 RTX Threads . 22 2.3 Conclusion . 23 vi 3 Mapping Methodology 25 3.1 Implementation and Verification Framework . 25 3.2 SysML Activity Diagrams Formalization . 26 3.3 JAVA Application Unit . 34 3.4 Summary . 38 4 Application 40 4.1 BART Case Study . 40 4.1.1 BART system overview . 40 4.1.2 Simulation and Verification in AF3 . 48 4.1.3 Implementation . 52 4.2 Thread Management in JPEG Encoder . 56 4.3 Summary . 61 5 Conclusion and Future work 63 5.1 Conclusion . 63 5.2 Future Work . 64 A BART train controller code 65 Bibliography 70 vii LIST OF TABLES 2.1 Technical information of CMSIS-RTOS RTX[34] . 24 3.1 Formalization of SysML Activity Diagram Artifacts . 27 4.1 Dublin to Daly City track properties . 43 4.2 Worst Case Scenario Distance parameters . 48 4.3 Worst Case Scenario Distance calculations . 49 viii LIST OF FIGURES 1.1 Verification artifacts and activities in AF3 . 4 1.2 Architecture of MARTE profile [43] . 5 1.3 Probabilistic Decision in SysML activity diagram . 6 1.4 Join two thread in SysML/UML activity diagram . 8 1.5 Mapping flowchart . 8 2.1 The taxonomy of UML structure and behavior diagrams [29] . 12 2.2 Relation between SysML and UML [32] . 14 2.3 The taxonomy of SysML structure [30] . 15 2.4 Activity Diagram Syntax . 16 2.5 Probabilistic Decision in SysML activity diagram . 18 2.6 Thread State and State Transitions[34] . 23 3.1 SysML to RTX verification and implementation framework . 26 3.2 SysMLToRTX.java Java application . 34 3.3 Simplified SysMLToRTX java application Class diagram . 35 4.1 The map of the BART transit system . 41 4.2 The Dublin/Pleasa track in BART transit system. 42 4.3 BART system modeled in AF3 . 50 4.4 TrainController module in AF3 . 51 4.5 Overview of verification platform . 52 4.6 Communication Packet Format . 52 4.7 Abstracted Computer Station model . 53 4.8 Simulation of BART train control system . 54 4.9 Calculation result from ComputerStation algorithm implemented in the FRDM board . 54 ix 4.10 Train Position over time . 55 4.11 Train acceleration over time . 56 4.12 Train Velocity over time . 56 4.13 Zigzag ordering of JPEG image components[47] . 58 4.14 JPEG Encoder pipeline . 58 4.15 Not scheduled JPEG encoder . 59 4.16 Not scheduled JPEG encoder output log file . 60 4.17 A scheduled JPEG encoder algorithm . 61 4.18 A scheduled JPEG encoder algorithm Output log . 62 x LIST OF ACRONYMS AATC Advance Automatic Train Control AF3 AutoFOCUS3 BART Bay Area Rapid Transit BSV Bluespec SystemVerilog CMSIS Cortex Microcontroller Software Interface Standard DCT Discrete Cosine Transform ESL Electronic System Level INCOSE International Council on Systems Engineering RTX Real Time eXecutive UML Unified Modeling Language MBSE Model Based System Engineers NuAC New Activity Calculus OMG Object Management Group OMT Object Modeling Technique PRISM PRobabilistIc Symbolic Model checker RTOS Real-Time Operating System SysML Systems Modeling Language WCSD Worst Case Scenario Distance xi Chapter 1 Introduction 1.1 Motivation The complexity in embedded systems has been increased in the last years. New heteroge- neous systems which combine different domains are more common. Aircrafts, automobiles, cell phones, medical equipment is an example where domains such as electronics, commu- nication, software, mechanics, physics, mathematics and medicine are part of the systems development today. The International Council on Systems Engineering (INCOSE)[1] iden- tified Model-Based Systems Engineering (MBSE) [2] as the key driver for effective and efficient system development in the future. Model-Based Design [3] is a technique for embedded system applications that reduces system complexity by creating a hierarchy of individual design blocks. OMG(Object Management Group) Systems Modeling Language (SysML) [4] was developed in order to support effective communication among the parties involved by means of a standardized graphical notation. SysML [5] is a standard modeling language used for system applications. It reuses a subset of UML packages [6]. Mainly, it covers four aspects of system modeling: structure, behavior, requirement, and parametric diagrams. SysML is composed of several diagram types (use case, activity, sequence and so on). Particularly, SysML activity diagrams[9] are graphical representations of work-flows of 1 step-wise activities and actions with support for choice, iteration and concurrency. In order to execute the SysML model in an embedded hardware platform, the SysML model needs to be mapped to low level C code. In this thesis, our main goal is to generate an executable C code from a SysML activity diagram model. Particularly, we are interested to automatically generate code for ARM CortexM processor family [10] from a SysML activity diagram model. To achieve this goal, a set of mapping rules are proposed that maps a SysML activity diagram into a correct code to be executed on ARM CortexM processor family.