ADDIS ABABA UNIVERSITY SCHOOL OF GRADUATE STUDIES FACULTY OF TECHNOLOGY DESIGN OF PULSE WIDTH MODULATION (PWM) AND IT’S IMPLEMENTATION IN XILINX FIELD PROGRAMMABLE GATE ARRAY (FPGA) A thesis submitted to the School of Graduate Studies of Addis Ababa University in partial fulfillment of the Degree of Masters of Science in Electrical Engineering By Teshome Ababu Advisor Prof. Dr.Gerald Higelin Addis Ababa Ethiopia February, 2007 ADDIS ABABA UNIVERSITY SCHOOL OF GRADUATE STUDIES FACULTY OF TECHNOLOGY DESIGN OF PULSE WIDTH MODULATION (PWM) AND IT’S IMPLEMENTATION IN XILINX FIELD PROGRAMMABLE GATE ARRAY (FPGA) BY Teshome Ababu Approval by Board of Examiners _Dr. Mengesha Mamo________________ ________________ Chairman (Department of graduate committee) Signature Prof.Dr.Gerald Higelin ________________ Advisor Signature Dr. Eneyew Adugna ________________ Interna Examiner Signature Dr. Goshal _________________ External Examiner Signature 2 DECLARATION I, the undersigned, hereby declare that this thesis is my original work performed under the supervision of Prof. Dr.Gerald Higelin has not been presented as a thesis for a degree program in any other university and all sources of materials used for the thesis are duly acknowledged. Name: Teshome Ababu Signature: ------------- Place: Addis Ababa Date of submission: --------------------- This thesis has been submitted for examination with our approval as university advisor. Prof. Dr.Gerald Higelin ---------------------- Signature Addis Ababa Ethiopia February 2007 3 Acknowledgments First and foremost, I would like to thank my advisor, Prof. Dr.Gerald Higelin for his inspiration and continuous support of my research, a great combination who is always willing to listen, encourage, and give insightful comments and valuable criticism. He read all the drafts of my thesis and taught me to be thorough in analyzing problems and rigorous in presenting ideas. This thesis would not have been possible without his support and guidance. I also thank my previous supervisor the late Prof. Dr.Santhanam A. who got me started in research. My gratitude is also conveyed to all my friends, for their cooperation and support during the time I studies. I am deeply grateful to my parents for their everlasting patience and love. I also would like to acknowledge the Xlinx FPGA Company for their valuable software and on line help. Finally, I would like to thank the almighty of God for helping me to complete this thesis. I all of thank you! 4 Table of Contents Page Acknowledgements . ……………………………………...i Abstract ………………………………………………………………………………………...ii List of Tables . ………………………………………..vi List of Figures . ……………………………………….vii Abbreviations . ……………………………………………………...ix Chapter 1: Introduction 1.1 Motivation…………………………………………………………………………1 1.2 Objective of the thesis……………………………………………………………..2 1.3 Thesis organization………………………………………………………………...3 Chapter 2: Literature Review 2.1 Pulse Width Modulation …………………………………………………5 2.2 Digital technology ………………………………………………………5 2.3 PWM Technique ……………………………………………………….7 Chapter 3: Programmable Logic Devices and VHDL 3.1 The History of Programmable Logic……………………………………………..11 3.2 Simple Programmable Logic Devices (SPLDs)…………………………………..13 3.3 Complex Programmable Logic Devices (CPLDs)………………………………..13 3.4 Field Programmable Gate Arrays (FPGAs)………………………………………15 3.4.1 FPGAs Architectures………………………………………………………...16 5 3.4.2 Xilinx SRAM-based FPGAs………………………………………………..18 3.4.3 Xilinx devices……………………………………………………………….21 3.4.4 Slices and CLBs…………………………………………………. 22 3.4.5 Advantage of FPGA……………………………………………………………..25 3.5 HDL………………………………………………………………………………..26 3.6 VHDL……………………………………………………………………………...27 3.6.1 The History of VHDL……………………………………………………...27 3.6.2 Design units………………………………………………………………..31 3.6.3 Levels of abstraction……………………………………………………….35 3.6.4 Signals and Variables……………………………………………………...36 3.6.5 Test benches………………………………………………………………..37 3.6.6 Advantages of VHDL………………………………………………………38 Chapter 4: Design of PWM in Xilinx FPGA 4.1 Xilinx ISE Overview…………………………………………………………….39 4.2 FPGA Design Flow ……………………………………………………………...41 4.3 Functional description of the PWM design ……………………………………...43 4.4 VHDL Modeling of the Functional description of PWM design………………...46 Chapter 5: Simulation results and discussion 5.1 XST synthesis …………………………………………………………………52 5.2 Viewing a Synthesis Report……………………………………………………53 5.3 Simulation Overview…………………………………………………………..58 6 5.4 Test benches …………………………………………………………………...58 5.5 Xilinx Synthesis and simulation results………………………………………..59 5.6 Simulation waveforms…………………………………………………………65 5.7 View technology schematic results……………………………………………67 Chapter 6: Conclusions & future work 6.1 Conclusions…………………………………………………………………..73 6.2 Future work…………………………………………………………………..73 Appendix A: VHDL Listing........................................................................................................75 References...................................................................................................................................80 7 List of Tables Table Page 5.1Device utilization summary………………………………………………………65 5.2 Some of the Data Values for different Duty Cycles (N=8)………………………65 5.3 PWM user interface signal description…………………………………………... 67 8 List of Figures Figure Page 2. 1 PWM signal with different duty cycles. ……………………………………..7 2.2 PWM Technique …………………………………………………………..8 2.3 Speed control of DC Motor using PWM…………………………………………….8 3.1 Digital logic technology…………………………………………………………….12 3.2 SPLD Architectures…………………………………………………………………13 3.3 CPLD Architecture…………………………………………………………………..4 3.4 FPGA Architecture………………………………………………………………….16 3.6 Xilinx XC4000 Configurable Logic Block (CLB)…………………………………..19 3.7Xilinx XC4000 Wire Segments………………………………………………………20 3.8. Slices………………………………………………………………………………...22 3.9. Simplified Slice structure……………………………………………………………23 3.10. Connecting Look-Up Tables……………………………………………………….24 3.11 VHDL block structure………………………………………………………………28 3.12 .VHDL-file structures……………………………………………………………….28 3.13 (a) Overview of entity and (b) Architecture syntax…………………………………29 3.14 Overview of architecture declarations……………………………………………….29 4.1 FPGA design flow…………………………………………………………………….39 4.2 FPGA Design methodology…………………………………………………………..41 4.3 functional block diagram of PWM……………………………………………………42 4.4 Pulse as a Function of the Count Value (ds = pwm_data)……………………………44 5.1 XST Design Flow Overview………………………………………………………….52 5.2 XST design flow………………………………………………………………………53 5.3 Waveform 1 pulse with 50% Duty cycle……………………………………………..66 9 5.4 Waveform 2: pulse with 25% Duty cycle…………………………………………….66 5.5 PWM user interface signal …………………………………………………………...67 5.6. RTL schematic view of PWM…………………………………………………………….68 5.7. (a) and (b) Equivalent Generic schematic of PWM of –MUX 0024-imp…………………69 5.8. (a) and (b) Technology schematic view of PWM…………………………………………71 5.9.The equivalent Look-up Table function generators of LUT 4 INT _OC09 in fig 5.8……..72 10 Abbreviations ASIC Application Specific Integrated Circuit ASSP Application Specific Standard Product CPLD Complex Programmable Logic Device CLB Configurable Logic Block CMOS Complimentary Metal Oxide Semiconductor FPGA Field Programmable Gate Array HDL Hardware description language I/O Inputs and Outputs ISE Integrated software environment ISP In-System Programming IEEE Institute of Electrical and Electronic Engineers JTAG Joint Test Action Group LUT Look Up Table MSI Midium Scale Integration NGC Xilinx specific netlist files OTP One time programmable PAL Programmable Array Logic device PLA Programmable Logic Array PLD Programmable Logic Device PWM Pulse Width Modulation RAM Random Access Memory RTL register transfer level SPLD Simple Programmable Logic Device SRAM Static Random Access Memory Tpd Time of Propagation Delay through the device TTL Transistor Transistor Logic 11 UUT Unit under test VHDL VHISC High Level Description Language VHSIC Very High Speed Integrated Circuit XST Xilinx Synthesis Technology XCF Xilinx constrains file 12 Abstract The following thesis describes the design, the synthesis, and the implementation of pulse width modulation (PWM) in Xilinx Field Programmable Gate Array (FPGA). The contribution of this thesis is the development of PWM in Xilinx Integrated System Environment (ISE) CAD tools and The VHDL modeling is used in the design process of PWM. Pulse width modulation has been widely used in many applications especially in communication and control systems. The paper develops high frequency PWM generator architecture for using FPGA. The resulting FPGA frequency depends on the target FPGA speed grade and the duty cycle resolution requirements. In most industrial application due to the need of design integration in control systems FPGA based PWM controller is advantageous over the other controller systems like microprocessor, microcontroller and so on. As geometries shrink and device counts multiply, opportunities abound to do incredible things with in the confines of a single chip (FPGA). Greater focus on design reuse, where earlier design is utilized and reused in later design. The power, compactness and flexibility of the FPGA based controller could be useful in motor control, particularly in robotics where those qualities are important. The FPGA provides advantages over traditional methods such as microcontroller based designs and PLD/ASIC designs by combining the strengths of both. The FPGA allows for implementation of parallel processing for generating the required waveforms. In addition