Reverse Costing® Structure, Process & Cost Analysis Second Generation of TSMC’s Integrated Fan-Out (inFO) Packaging for the Apple A11 found in the iPhone X The latest Apple application processor engine : from the stacked board to the A11, and reverse costing of TSMC's updated inFO packaging Title: Apple A11 inFO- PoP Pages: 140 Date: February 2018 Format: PDF & Excel file Price: Full report: EUR 3,490 Until 2015, Apple used to integrate its application processor engine (APE) in standard Package-on-Package (PoP) packaging. Starting in 2016, with the Apple A10 APE in the Apple iPhone 7, TSMC has brought a breakthrough fan-out technology called integrated Fan-Out (inFO) packaging to the market. This is still the most innovative, COMPLETE TEARDOWN powerful and cost-effective fan-out packaging technology for the APE. For its latest WITH: flagships, the Apple iPhone 8 and tenth’s anniversary iPhone X, Apple has renewed • Detailed photos: its collaboration with TSMC by using the new generation of inFO packaging for the cross-sections Apple A11 APE. • Precise Comparing the iPhone X and the iPhone 8, Apple and its partners have integrated the measurements two flagships’ main boards differently. In the iPhone X, the main board uses special • Materials analysis printed circuit board (PCB) technology from AT&S to reduce its PCB footprint by about • Manufacturing 15%. To do this, AT&S uses two stacked PCBs with components mounted on both sides process flow and a via frame. The APE is located inside the structure, under the DRAM package, using PoP technology. This new version also features new land-side decoupling • Supply chain capacitor (LSC) technology. evaluation • Manufacturing cost The Apple A11 is a wafer-level package using the new generation of TSMC’s packaging analysis technology. It uses copper pillars, called Through inFO Vias (TiVs), to replace the well- known Through Molded Via (TMV) technology. Apple still outperforms standard PoP • Estimated sales price technology thanks to the inFO packaging and its innovations, which include copper • Technology pillars, redistribution layers and silicon high density capacitor integration. comparison with standard PoP, This report analyzes the complete package, from the DRAM memory to the LSC Shinko’s MCeP PoP developed by TSMC. The report includes a comprehensive cost analysis and price and TSMC’s inFO first estimation of the device based on detailed description of the packaging. It also features generation a detailed technology comparison with standard PoP and Shinko’s MCeP PoP packaging. TABLE OF CONTENTS Overview/Introduction Manufacturing Process Flow • Packaging Fabrication Unit AUTHORS: Apple Company Profile and • inFO Package Process Flow inFO Technology • Deep Trench Capacitor (DTC) Chip Fabrication Unit Dr. Stéphane Apple iPhone 8 and iPhone X E l i s a b e t h • DTC Process Flow Teardown Stéphane has a Cost Analysis deep knowledge Physical Analysis • Summary of the Cost Analysis of materials • Physical Analysis characterizations Methodology • Supply Chain Description and electronics systems. He holds • Yield Hypotheses • A11 Packaging Analysis an Engineering Degree in Package view and • A11 Die Cost Analysis Electronics and Numerical dimensions: X-ray, RDL Wafer cost Technology, and a PhD in deprocessing, RDL Die cost Materials for Microelectronics. line/space width • DTC Die Cost Analysis Package opening: DRAM Wafer cost memories, APE die Die cost Nicolas Radufe Board and package cross- • inFO Package Cost Analysis (Lab) section: via frame, main inFO wafer front-end cost board PCB, TiV, adhesives, Ni co l a s is in RDLs inFO cost per process step c h a r g e of • Land-Side Decoupling • Final Test Cost p h y s i c a l Capacitor • Component Cost analysis. He has a deep knowledge in chemical Die view and dimensions Estimated Price Analysis and physical analyses. He Die overview and previously worked in delayering microelectronics R&D for Die cross-section Technology comparison with CEA/LETI in Grenoble and for Die process Samsung’s PoP, Shinko’s MCeP and the previous inFO STMicroelectronics in Crolles. generation from the Apple A10 ANALYSIS PERFORMED WITH OUR COSTING TOOL 3D PACKAGE COSIM+ System Plus Consulting offers powerful costing tools to evaluate the production cost and selling price from single chip to complex structures. 3D Package Cosim+ 3D Package CoSim+ Cost simulation tool to evaluate the cost of any Packaging process: Wafer- level packaging, TSV, 3D integration… Performed by RELATED REPORTS NXP SCM-i.MX6 Quad High Qualcomm VIVE® QCA9500 TSMC Integrated Fan-Out Density Fan-Out Wafer-Level High Density WiGig/WiFi (inFO) Package in Apple’s A10 System-in-Package 802.11ad Chipset for the 60 Application Processor GHz Band The first ultra-small multi-die low Disruptive double side molded Reverse engineering and costing of power module with boot memory system-in-package-based chipset for the new inFOpackaging technology and power management integrated millimeter-wave applications from TSMC used for Apple’s latest in a package-on-package targeting consumer devices, A10 application processor, found in compatible device for the Internet including integrated antennae. the iPhone 7 and 7 Plus. of Things. Pages: 132 Pages: 145 Pages: 100 Date: June 2017 Date: January 2018 Date: October 2016 Full report: EUR 3,490* Full report: EUR 3,990* Full report: EUR 3,490* ANNUAL SUBSCRIPTION OFFER Each year System Plus Consulting releases a comprehensive collection of new reverse engineering & costing analyses in various domains. You can choose to buy over 12 months a set of 3, 4, 5, 7, 10 or 15 Reverse Costing® reports. Up to 47% discount! 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