Louisiana State University LSU Digital Commons LSU Doctoral Dissertations Graduate School 2005 Techniques for low power analog, digital and mixed signal CMOS integrated circuit design Chuang Zhang Louisiana State University and Agricultural and Mechanical College, [email protected] Follow this and additional works at: https://digitalcommons.lsu.edu/gradschool_dissertations Part of the Electrical and Computer Engineering Commons Recommended Citation Zhang, Chuang, "Techniques for low power analog, digital and mixed signal CMOS integrated circuit design" (2005). LSU Doctoral Dissertations. 852. https://digitalcommons.lsu.edu/gradschool_dissertations/852 This Dissertation is brought to you for free and open access by the Graduate School at LSU Digital Commons. It has been accepted for inclusion in LSU Doctoral Dissertations by an authorized graduate school editor of LSU Digital Commons. For more information, please [email protected]. TECHNIQUES FOR LOW POWER ANALOG, DIGITAL AND MIXED SIGNAL CMOS INTEGRATED CIRCUIT DESIGN A Dissertation Submitted to the Graduate Faculty of the Louisiana State University and Agricultural and Mechanical College in partial fulfillment of the requirements for the degree of Doctor of Philosophy in The Department of Electrical and Computer Engineering by Chuang Zhang B.S., Tsinghua University, Beijing, China. 1997 M.S., University of Southern California, Los Angeles, U.S.A. 1999 M.S., Louisiana State University, Baton Rouge, U.S.A. 2001 May 2005 ACKNOWLEDGEMENTS I would like to dedicate my work to my parents, Mr. Jinquan Zhang and Mrs. Lingyi Yu and my wife Yiqian Wang, for their constant encouragement throughout my life. I am very grateful to my advisor Dr. Ashok Srivastava for his guidance, patience and understanding throughout this work. His suggestions, discussions and constant encouragement have helped me to get a deep insight in the field of Mixed Signal IC design. I would like to thank Dr. Pratul K. Ajmera for being Co-Chair of my committee. I would like to thank Dr. Martin Feldman, Dr. J. Ramanujam, Dr. Bhaba R. Sarker and Dr. Sukhamay Kundu for being a part of my committee. I would like to thank Dr. Dongsheng Ma for his help in DC/DC converter design. I am very thankful to Electrical & Computer Engineering Department and to Louisiana State University for the Louisiana Economic Development Assistantship, for supporting me financially during my stay at LSU. This work is also supported by NSF- EPSCoR under contract No. 0092001. I take this opportunity to thank my friends Tinghui, Chi, Anand for their help and encouragement at times when I needed them. I would also like to thank all my friends here who made my stay at LSU an enjoyable and a memorable one. Last of all I thank God for keeping my family in good health and spirits throughout my stay at LSU. ii TABLE OF CONTENTS ACKNOWLEDGEMENTS..............................................................................................ii LIST OF TABLES.............................................................................................................v LIST OF FIGURES..........................................................................................................vi ABSTRACT...................................................................................................................... xi CHAPTER 1. INTRODUCTION.................................................................................... 1 1.1 FORWARD BODY-BIAS METHOD ................................................................................ 5 1.2 NOISE OF FORWARD BODY-BIAS MOSFET .................................................................. 9 1.3 DYNAMIC THRESHOLD MOSFET .............................................................................. 10 1.4 ADAPTIVE BODY-BIAS GENERATOR ........................................................................ 14 1.5 DYNAMIC VOLTAGE SCALING ................................................................................. 15 1.6 GOALS AND OBJECTIVES ......................................................................................... 18 CHAPTER 2. FORWARD BODY-BIAS TECHNIQUE ............................................ 20 2.1 THRESHOLD VOLTAGE OF THE MOSFET................................................................... 20 2.2 FORWARD BODY-BIAS ............................................................................................ 24 2.3 AMPLIFIER DESIGN USING FORWARD BODY-BIAS TECHNIQUE ................................. 29 2.3.1 A Two-Stage CMOS Amplifier Topology.................................................. 29 2.3.2 Low Voltage Current Mirrors Design.......................................................... 32 2.3.3 Low Voltage Operational Amplifier Design................................................ 36 2.3.4 Simulation and Experimental Results.......................................................... 47 2.4 SUMMARY .............................................................................................................. 47 CHAPTER 3. NOISE ANALYSIS OF A FORWARD BODY-BIAS CMOS AMPLIFIER ................................................................................................................... 54 3.1 NOISE IN THE MOSFET............................................................................................. 54 3.2 NOISE IN A FORWARD BODY-BIASED N-MOSFET ...................................................... 55 3.3 NOISE ANALYSIS OF A FORWARD BODY-BIAS CMOS AMPLIFIER CIRCUIT ................. 61 3.4 SUMMARY .............................................................................................................. 65 CHAPTER 4. DYNAMIC THESHOLD MOSFET TECHNIQUE ........................... 68 4.1 IMPROVED DTMOS INVERTER.................................................................................. 71 4.2 A LOW VOLTAGE ANALOG MULTIPLEXER DESIGN USING DTMOS TECHNIQUE .......... 73 4.3 LOW VOLTAGE CMOS SCHMITT TRIGGER INTEGRATED CIRCUITS............................. 79 4.4 SUMMARY .............................................................................................................. 92 CHAPTER 5. ADAPTIVE BODY-BIAS GENERATOR CIRCUIT......................... 97 5.1 A CMOS BODY-BIAS GENERATOR CIRCUIT DESIGN .................................................. 98 5.2 REDUCTION OF LEAKAGE CURRENT ...................................................................... 107 5.3 EXPRIMENTAL RESULTS........................................................................................ 111 5.4 SUMMARY ............................................................................................................ 111 iii CHAPTER 6. ADAPTIVE DC/DC CONVERTER................................................... 118 6.1 DC/DC CONVERTER WITH DELAY-LINE BASED CONTROLLER................................. 119 6.2 PROPOSED ADAPTIVE PULSE-TRAIN TECHNIQUE.................................................... 123 6.3 SUMMARY ............................................................................................................ 140 CHAPTER 7. CONCLUSION AND SCOPE FOR FUTURE WORK.................... 141 7.1 FORWARD BODY-BIAS TECHNIQUE AND CMOS AMPLIFIER..................................... 141 7.2 NOISE IN THE FORWARD BODY-BIAS MOSFET ........................................................ 141 7.3 DYNAMIC THRESHOLD MOSFET TECHNIQUE AND NOVEL SCHMITT TRIGGER CIRCUITS .............................................................................................................. 142 7.4 ADAPTIVE BODY-BIAS GENERATOR ...................................................................... 142 7.5 DYNAMIC VOLTAGE SCALING AND DC/DC CONVERTER ......................................... 143 7.6 SCOPE FOR FUTURE WORK .................................................................................... 144 REFERENCES.............................................................................................................. 145 APPENDIX A. MOSIS SPICE LEVEL 3 MOS MODEL PARAMETERS FOR A STANDARD N-WELL CMOS TECHNOLOGY...................................................... 149 APPENDIX B. MOSFET MODELING...................................................................... 150 APPENDIX C. MEASURMENT OF AMPLIFIER PARAMETERS [35].............. 158 C.1 OP-AMP INPUT OFF-SET VOLTAGE (VOS) ................................................................ 158 C.2 COMMON MODE REJECTION RATIO (CMRR)........................................................... 158 C.3 POWER SUPPLY REJECTION RATIO (PSSR) ............................................................. 162 C.4 INPUT COMMON MODE RANGE (ICMR) .................................................................. 162 C.5 SLEW RATE (SR) ................................................................................................... 162 APPENDIX D. LIST OF PUBLICATIONS............................................................... 167 VITA............................................................................................................................... 168 iv LIST OF TABLES Table 2.1: W/L ratios of transistors in CMOS amplifier circuit of Fig. 2.13 ................... 41 Table 2.2: Measured and simulated parameters of the CMOS amplifier circuit of Fig. 2.13.................................................................................................................. 52 Table 2.3: A comparative study of the present amplifier characteristics with the corresponding parameters reported in recent publications. ............................ 53 Table 5.1: Truth