7 Series FPGAs Configurable Logic Block User Guide UG474 (v1.8) September 27, 2016 DISCLAIMER The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. 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Revision History The following table shows the revision history for this document. Date Version Revision 03/01/2011 1.0 Xilinx Initial release. 03/28/2011 1.1 Added devices XC7K355T, XC7K420T, and XC7K480T to Table 1-3. Portions of the text have been revised for clarity. 09/30/2011 1.2 Added last sentence under 7 Series CLB Features. Added Table 1-3 and Table 1-4. Updated CLB features in Table 1-3. Added first sentence under CLB Arrangement, added ASMBL Architecture section, and CLB Slices heading. Added last paragraph under Carry Logic. Added lasts sentence under Using Carry Logic. Added second sentence under Slice Multiplexer Timing Parameters. Modified Table 5-2, Table 5-4, and Table 5-5 for clarity. Added Devices Using Stacked Silicon Interconnect (SSI) Technology section. 01/30/2012 1.3 Revised Table 1-2. Added fifth paragraph under Distributed RAM (Available in SLICEM Only). Clarified last paragraph under Global Controls GSR and GTS. 11/05/2012 1.4 Changed “uniformity” to “optimized” in last bullet under 7 Series CLB Features. Changed “unified” to “scalable” in first sentence under Device Resources. Deleted 7A350T device from Table 1-2. Deleted 7V1500T and 7VH290T devices from Table 1-4. Added reference to 7 Series FPGA Libraries Guide to Distributed RAM (Available in SLICEM Only), Shift Registers (Available in SLICEM Only), and Flip-Flop Primitives. Changed “TCEO” to “TCECK” in Figure 5-2 and first bullet under General Timing Characteristics. 7 Series FPGAs CLB User Guide www.xilinx.com UG474 (v1.8) September 27, 2016 Date Version Revision 08/6/2013 1.5 Added Artix®-7 devices. Updated references to implementation tools. 08/11/2014 1.6 Revised footnotes in Table 1-2 through Table 1-4. Revised polarity from independent to programmable in Control Signals, page 22. Added Primitive column to Table 2-3 and removed footnotes. Renamed or made minor revisions to Figure 2-6 through Figure 2-14. Revised sections Clock – WCLK, page 49, Clock – CLK, page 50, and Clock - C, page 51. 11/17/2014 1.7 Updated Table 1-2 for new Artix 7A15T device. 09/27/2016 1.8 Added Spartan®-7 device family (updated Preface and added Table 1-1). Added Artix®-7 7A12T and 7A25T devices to Table 1-2. UG474 (v1.8) September 27, 2016 www.xilinx.com 7 Series FPGAs CLB User Guide 7 Series FPGAs CLB User Guide www.xilinx.com UG474 (v1.8) September 27, 2016 Table of Contents Revision History . 2 Preface: About This Guide Guide Contents . 7 Additional Support Resources. 8 Chapter 1: Overview CLB Overview . 9 7 Series CLB Features . 10 Device Resources . 10 Recommended Design Flow. 12 Pinout Planning. 13 Chapter 2: Functional Details CLB Arrangement . 15 Slice Description . 18 Look-Up Table (LUT) . 21 Storage Elements. 21 Distributed RAM (Available in SLICEM Only) . 23 Shift Registers (Available in SLICEM Only) . 34 Multiplexers . 39 Carry Logic . 43 Chapter 3: Design Entry Design Checklist . 45 Using the CLB Resources. 46 Primitives. 46 Chapter 4: Applications Distributed RAM Applications . 53 Shift Register Applications. 53 Carry Logic Applications . 55 Chapter 5: Timing CLB General Slice Timing Model and Parameters. 58 CLB Slice Multiplexer Timing Model and Parameters. 60 CLB Slice Carry-Chain Timing Model and Parameters . 61 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback 5 UG474 (v1.8) September 27, 2016 CLB Slice Distributed RAM Timing Model and Parameters (Available in SLICEM Only) 63 CLB Slice SRL Shift Register Timing Model and Parameters (Available in SLICEM Only) . 66 Chapter 6: Advanced Topics Using the Latch Function as Logic . 71 Interconnect Resources . 72 Devices Using Stacked Silicon Interconnect (SSI) Technology . 73 6 Send Feedback www.xilinx.com 7 Series FPGAs CLB User Guide UG474 (v1.8) September 27, 2016 Preface About This Guide Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power to enable a common design to scale across families for optimal power, performance, and cost. The Spartan®-7 family is the lowest density with the lowest cost entry point into the 7 series portfolio. The Artix®-7 family is optimized for highest performance-per-watt and bandwidth-per-watt for cost-sensitive, high-volume applications. The Kintex®-7 family is an innovative class of FPGAs optimized for the best price-performance. The Virtex®-7 family is optimized for highest system performance and capacity. This guide serves as a technical reference describing the 7 series FPGAs configurable logic blocks (CLBs). Usually, logic synthesis assigns the CLB resources without system designer intervention. It can be advantageous for the designer to understand certain CLB details, including the varying capabilities of the look-up tables (LUTs), the physical direction of the carry propagation, the number and distribution of the available flip-flops, and the availability of the very efficient shift registers. This guide describes these and other features of the CLB in detail. This 7 Series FPGAs Configurable Logic Block User Guide, part of an overall set of documentation on the 7 series FPGAs, is available on the xilinx.com/documentation. Guide Contents This manual contains these chapters: • Chapter 1, Overview, provides basic information needed for the majority of users, including: • CLB Overview is targeted at the new user. • 7 Series CLB Features discusses what is new compared with the Spartan®-6 and Virtex®-6 FPGA families for the experienced user and provides design migration considerations. • Device Resources indicates the number of resources per device, and unity between different 7 series families. • Recommended Design Flow provides the basics of using CLB resources and lists key aspects to consider. • Pinout Planning discusses aspects of CLBs that might affect pin placement for a design. • Chapter 2, Functional Details, lists architectural specifics for each CLB feature. • Chapter 3, Design Entry, provides design entry guidelines and primitives for instantiation. • Chapter 4, Applications, provides examples that use the CLB resources in larger applications. 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback 7 UG474 (v1.8) September 27, 2016 Preface: About This Guide • Chapter 5, Timing, contains timing models and defines CLB timing specifications from the respective 7 series FPGA data sheet. • Chapter 6, Advanced Topics, discusses advanced features of the 7 series CLB. Additional Support Resources To find additional documentation, see the Xilinx website at: http://www.xilinx.com/support.html#documentation To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: www.xilinx.com/support 8 Send Feedback www.xilinx.com 7 Series FPGAs CLB User Guide UG474 (v1.8) September 27, 2016 Chapter 1 Overview CLB Overview The 7 series configurable logic block (CLB) provides advanced, high-performance FPGA logic: • Real 6-input look-up table (LUT) technology • Dual LUT5 (5-input LUT) option • Distributed Memory and Shift Register Logic capability • Dedicated high-speed carry logic for arithmetic functions • Wide multiplexers for efficient utilization CLBs are the main logic resources for implementing sequential as well as combinatorial circuits.