Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories Adam Teman∗, Georgios Karakonstantis∗, Robert Giterman†, Pascal Meinerzhagen‡, Andreas Burg∗ ∗ Telecommunications Circuits Lab (TCL), Ecole´ Polytechnique Fed´ erale´ de Lausanne (EPFL), Switzerland † Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel ‡ Circuit Research, Intel Labs, JF3-334, 2111 NE 25th Ave, Hillsboro, OR 97124 Email: {adam.teman, georgios.karakonstantis, andreas.burg}@epfl.ch Abstract—Current variation aware design methodologies, silicon predictability reduces with technology scaling, putting tuned for worst-case scenarios, are becoming increasingly pes- the feasibility of such a design approach in doubt [6]. simistic from the perspective of power and performance. A good This reality has led to the quest for alternative de- example of such pessimism is setting the refresh rate of DRAMs according to the worst-case access statistics, thereby resulting sign strategies and to the promising approximate computing in very frequent refresh cycles, which are responsible for the paradigm [6]–[8], in which the error resilient nature of many majority of the standby power consumption of these memories. applications is exploited to relax the design constraints and However, such a high refresh rate may not be required, either save power. The approximate computing paradigm includes due to extremely low probability of the actual occurrence of the development of processors and software that may not such a worst-case, or due to the inherent error resilient nature of many applications that can tolerate a certain number of potential always produce 100% precise results, but their output fidelity failures. In this paper, we exploit and quantify the possibilities is acceptable for human consumption at a significantly reduced that exist in dynamic memory design by shifting to the so-called power [6]–[8]. Error resilient applications also open up possi- approximate computing paradigm in order to save power and bilities in dynamic memory design, providing an opportunity enhance yield at no cost. The statistical characteristics of the to potentially reduce the memory refresh rate, without caring retention time in dynamic memories were revealed by studying a fabricated 2 kb CMOS compatible embedded DRAM (eDRAM) about a certain extent of resulting failures [9], [10]. However, memory array based on gain-cells. Measurements show that up this raises questions regarding the yet to be quantified energy to 73% of the retention power can be saved by altering the vs. reliability trade offs in eDRAM, and if such a paradigm refresh time and setting it such that a small number of failures can be realized and lead to more efficient operation. is allowed. We show that these savings can be further increased In this paper, we try to address these questions by investi- by utilizing known circuit techniques, such as body biasing, which can help, not only in extending, but also in preferably gating the viability of the idea for a paradigm shift in gain- shaping the retention time distribution. Our approach is one of cell based embedded DRAM (GC-eDRAM). These memories the first attempts to access the data integrity and energy trade- have been gaining attention in the research community, due offs achieved in eDRAMs for utilizing them in error resilient to features such as small cell size, low leakage, and logic applications and can prove helpful in the anticipated shift to compatibility [2], [3], [5], [11], [12]. As a basis for our approximate computing. analysis, we use the retention time of a fabricated 2T gain- Index Terms —Embedded Memories, DRAM, Refresh Power, cell array, which has been characterized across several chips, Data Integrity, Energy Efficiency, Error Resilience allowing us to extract the failure probability as a function of I. INTRODUCTION the refresh rate. Our measurements not only reveal the large The large amount of data that needs to be handled by to- spread of retention time in GC-eDRAM, but also its graceful day’s systems has increased the memory requirements, which degradation, which is a preferred characteristic for relaxing already often occupy more than 50% of silicon real-estate the refresh rate and promoting the proposed approximate and power in embedded systems [1]. This has led to a rise storage idea. In particular, this means that only very few cells in popularity of embedded dynamic-random-access-memory have short retention times and the error probability increases (eDRAMs) due to their high-density and low retention power, monotonically and slowly as the refresh rate is decreased. This as compared to static random access memory (SRAM) [2]– allows to save a significant amount of refresh power with only [5]. However, eDRAMs still require periodic, power-hungry a small number of failures that can be limited to the tolerance refresh cycles to retain the stored data. Traditional design threshold of a particular error resilient application. approaches dictate that the frequency of these refresh cycles is Contributions: Our study advances recent works [9], [13] determined by the worst-case retention time of the most leaky that have attempted to exploit the error resilient nature of cell. While such an approach guarantees error-free storage, it various applications for implementing approximate DRAM results in high refresh power consumption, most of which is storage by revealing the actual DRAM characteristics. Such wasted due to the extremely rare occurrence of pessimistically early works were not able to reveal the actual statistical assumed worst-case conditions [5]. The design margins and characteristics of the retention time since they were based resulting wasted power is expected to further increase as mainly on high-level models of DRAM cells and focused on their utilization within simulators at the microarchitecture and This work was partially supported by the EU OPEN-FET SCoRPiO grant (no. 323872), the EU Marie-Curie DARE grant (no. 304186) and the ICYSoC software layer. Our contributions can be summarized as: RTD project (no. 20NA21 150939) funded by Nano-Tera.ch. • Characterization of the retention time of a silicon fab- 978-3-9815370-4-8/DATE15/c 2015 EDAA 489 write assertion WWL read sensing MW MR read ‘0’ SN read ‘1’ VB VB =write ‘0’ =write ‘1’ CSN read assertion RBL DD GND V WBL RWL Fig. 1. (a) Schematic of all-PMOS 2T Gain Cell. (b) Operation waveforms. ricated 2 kb GC-eDRAM array, revealing a large spread both within a single array and across different chips. • Analysis of the wasted power, assuming that the tradi- Fig. 2. Level degradation of an all-PMOS 2T GC-eDRAM bitcell over 1 k tional worst-case cell criterion is used to determine the MC samples in a CMOS 0.18 μm process. refresh rate. • Discussion of an alternative criterion for determining the GC-eDRAM1, shown in Fig. 1 [2], [5], [11], [12]. This cell refresh rate, and analysis of the potential power savings comprises a write transistor (MW), a read transistor (MR), by applying it. We show that the failure rate increases and a storage node (SN) made up of the parasitic capacitance gracefully with reduction of the refresh rate, thereby of the devices and their connecting wires. Typical operational obtaining large power savings, while keeping the number waveforms are illustrated in Fig. 1 for write and read access of failures under application tolerable levels. cycles for both ‘0’ and ‘1’ data. Write operations are initiated • Utilization of other circuit level techniques, such as the by biasing the write bitline (WBL) at VDD (‘1’) or GND application of body bias, to shift the retention time distri- (‘0’), and subsequently pulsing the write word line (WWL) bution in order to increase the potential power savings and to a negative voltage, thereby charging or discharging the SN. favorably shape it to better exploit the previous methods. Subsequently, a read operation can be initiated by discharging • Analysis of yield improvement through error tolerance, the read bitline (RBL) and pulsing the read word line (RWL) assuming a fixed refresh rate and power requirement. to VDD. Depending on the voltage level stored in the cell, The rest of the paper is organized as follows: Section MR is either cutoff (in case of a ‘1’) or conducting (in case II describes the operation of GC-eDRAM and analyzes the of a ‘0’). Therefore, RBL remains discharged or is charged, retention time of a fabricated array. Section III discusses respectively, and amplified to a digital output level. the wasted power due to traditional worst-case design. The As with all dynamic circuits, the level stored on the internal proposed approach and trade-offs between error probability capacitance of a GC-eDRAM cell degrades over time. In the and power savings are presented in Section IV, including yield case of the all-PMOS 2T cell, the dominant leakage current has improvement through error tolerance. Section V discusses been shown to be the subthreshold (sub-VT) current through circuit level techniques for achieving further power savings MW [5], [11], given by: and improve the efficacy of the proposed idea. Finally, Section VSG,MW−|VT,MW| VSD,MW ηVSD,MW IMW = I0e nφt (1 − e nφt )e nφt , (1) VI concludes the paper. where VSG,MW, VSD,MW, and VT,MW are the source-to-gate, II. GAIN CELL BASED EDRAM AND DATA RETENTION source-to-drain, and threshold voltages, respectively, of MW; φt is the thermal voltage; n is the sub-VT slope; and η is the GC-eDRAM is a low-cost, high-density alternative to drain-induced barrier lowering (DIBL) coefficient. SRAM for the implementation of on-chip, logic-compatible The SN level degradation is simulated in Fig. 2 for 1000 embedded memories, without the need for additional process Monte Carlo (MC) samples of initially stored ‘0’ and ‘1’ levels steps.