ECE1371 Advanced Analog Circuits Course Goals Lecture 1 • Deepen understanding of CMOS analog circuit design through a top-down study of a modern INTRODUCTION TO analog system The lectures will focus on Delta-Sigma ADCs, but DELTA-SIGMA ADCS you may do your project on another analog system. • Develop circuit insight through brief peeks at some nifty little circuits The circuit world is filled with many little gems that Richard Schreier every competent designer ought to recognize. [email protected] Trevor Caldwell [email protected] ECE1371 1-2 Logistics Date Lecture Ref Homework 2008-01-07 RS 1 Introduction: MOD1 & MOD2 S&T 2-3, A Matlab MOD2 • Format: 2008-01-14 RS 2 Example Design: Part 1 S&T 9.1, J&M 10 Switch-level sim Meet Mondays 3:00-5:00 PM 2008-01-21 RS 3 Example Design: Part 2 J&M 14 Q-level sim except Feb 4 and Feb 18 2008-01-28 TC 4 Pipeline and SAR ADCs Arch. Comp. 12 2-hr lectures 2008-02-04 ISSCC– No Lecture plus proj. presentation 2008-02-11 RS 5 Advanced ∆Σ S&T 4, 6.6, 9.4, B CTMOD2; Proj. 2008-02-18 Reading Week– No Lecture • Grading: 2008-02-25 RS 6 Comparator & Flash ADC J&M 7 40% homework 2008-03-03 TC 7 SC Circuits J&M 10 60% project 2008-03-10 TC 8 Amplifier Design • References: 2008-03-17 TC 9 Amplifier Design Schreier & Temes, “Understanding ∆Σ …” 2008-03-24 TC 10 Noise in SC Circuits S&T C Johns & Martin, “Analog IC Design” 2008-03-31 Project Presentation Razavi, “Design of Analog CMOS ICs” 2008-04-07 TC 11 Matching & MM-Shaping Project Report 2008-04-14 RS 12 Switching Regulator Q-level sim Lecture Plan: ECE1371 1-3 ECE1371 1-4 NLCOTD: Level Translator What is ∆Σ? VDD1 > VDD2, e.g. • ∆Σ is NOT a fraternity It is more like a way of life… 3-V logic ? 1-V logic • Simplified ∆Σ ADC structure: • VDD1 < VDD2, e.g. Analog Loop Coarse Digital In Filter ADC Out (to digital 1-V logic ? 3-V logic filter) DAC • Constraints: CMOS 1-V and 3-V devices no static current • Key features: coarse quantization, filtering, feedback and oversampling Quantization is often quite coarse: 1 bit! ECE1371 1-5 ECE1371 1-6 What is Oversampling? Oversampling Simplifies AAF Desired Undesired • Oversampling is sampling faster than required OSR ~ 1: Signal Signals by the Nyquist criterion For a lowpass signal containing energy in the (), frequency range0 f B , the minimum sample rate required for perfect reconstruction is f s = 2f B f ≡ ⁄ () f ⁄ 2 • The oversampling ratio is OSR f s 2f B s First alias band is very close OSR = 3: Wide transition band • For a regular ADC, OSR ∼ 23– To make the anti-alias filter (AAF) feasible • For a ∆Σ ADC, OSR ∼ 30 To get adequate quantization noise suppression. f All signals abovef are removed digitally. ⁄ B f s 2 Alias far away ECE1371 1-7 ECE1371 1-8 How Does A ∆Σ ADC Work? A ∆Σ DAC System ⇒ 1 • Coarse quantization lots of quantization error. t So how can a ∆Σ ADC achieve 22-bit resolution? –1 ∆Σ •A ADC spectrally separates the quantization digital uv∆Σ Reconstruction w analog error from the signal through noise-shaping input Modulator Filter output (interpolated) 1 bit @fs 1 analog t signal shaped output t –1 noise ∆Σ ⁄ ⁄ analog uvDecimation w digital f B f s 2 f B f s 2 f B f s input ADC Filter output 1 bit @fs n@2fB desired • Mathematically similar to an ADC system signal Nyquist-rate Except that now the modulator is digital and drives a undesired shaped signals noise PCM Data low-resolution DAC, and that the out-of-band noise is ⁄ ⁄ handled by an analog reconstruction filter. f B f s 2 f B f s 2 f B ECE1371 1-9 ECE1371 1-10 Why Do It The ∆Σ Way? Highlights • ADC: Simplified Anti-Alias Filter (i.e. What you will learn today) Since the input is oversampled, only very high 11st- and 2nd-order modulator structures and frequencies alias to the passband. These can often theory of operation be removed with a simple RC section. If a continuous-time loop filter is used, the anti-alias 2 Inherent linearity of binary modulators filter can often be eliminated altogether. 3 Inherent anti-aliasing of continuous-time • DAC: Simplified Reconstruction Filter modulators The nearby images present in Nyquist-rate 4 Spectrum estimation with FFTs reconstruction can be removed digitally. + Inherent Linearity Simple structures can yield very high SNR. + Robust Implementation ∆Σ tolerates sizable component errors. ECE1371 1-11 ECE1371 1-12 Background Poor Man’s ∆Σ DAC (Stuff you already know) Suppose you have low-speed 16-bit data and • The SQNR* of an ideal n-bit ADC with a full-scale a high-speed 8-bit DAC sine-wave input is (6.02n + 1.76) dB • How can you get good analog performance? “6 dB = 1 bit” • The PSD at the output of a linear system is the product of the input’s PSD and the squared magnitude of the system’s frequency response 16-bit data 16 8 Good DAC Quality i.e. XY j 2πf 2 ⋅ @ 50 kHz ? H(z) Syy()f = He()Sxx()f Audio • The power in any frequency band is the integral of the PSD over that band 5 MHz *. Signal-to-Quantization-Noise Ratio ECE1371 1-13 ECE1371 1-14 Simple (-Minded) Solution Spectral Implications • Only connect the MSBs; leave the LSBs hanging Desired Signal Unwanted Images 16 MSBs 8 DAC sin()x ------------------ DAC frequency response @50 kHz LSBs x 8 5 MHz (or 50 kHz) Frequency 25 kHz DAC Output 16-b Input Data Quantization Noise @ 8-bit level ⇒ SQNR = 50 dB 20 us Time ECE1371 1-15 ECE1371 1-16 Better Solution Spectral Implications • Exploit oversampling: Clock fast and add dither • Quantization noise is now spread over a broad frequency range 16 8 Oversampling reduces quantization noise density DAC @50 kHz 8 8 @ 5 MHz 2.5 MHz OSR ==---------------------- 100 → 20 dB dither spanning 25 kHz one 8-bit LSB 5 MHz DAC Output 16-b Input Data Frequency 25 kHz 2.5 MHz In-band quantization noise power = 1% of total quantization noise power Time ⇒ SQNR = 70 dB ECE1371 1-17 ECE1371 1-18 Even More Clever Method Mathematical Model • Add LSBs back into the input data • Assume the DAC is ideal, model truncation as the addition of error: 16 8 E = –LSBs DAC @50 kHz @ 5 MHz 8 U V = U + (1–z–1)E z–1 5 MHz z-1 –E DAC Output • Hmm… Oversampling, coarse quantization and 16-b Input Data feedback. Noise-Shaping! • Truncation noise is shaped by a 1–z–1 transfer function, which provides ~35 dB of attenuation Time in the 0-25 kHz frequency range ECE1371 1-19 ECE1371 1-20 Spectral Implications MOD1: 1st-Order ∆Σ Modulator • Quantization noise is heavily attenuated at low Standard Block Diagram frequencies ∆ Σ Quantizer “ ”“” (1-bit) v Y 1 UVQ y Shaped –1 Quantization Noise z-1 Feedback Frequency -1 V’ DAC v’ 25 kHz 2.5 MHz z DAC v In-band quantization noise power is very small, 55 dB below total power Since two points define a line, ⇒ SQNR = 105 dB! a binary DAC is inherently linear. ECE1371 1-21 ECE1371 1-22 MOD1 Analysis The Noise Transfer Function • Exact analysis is intractable for all but the • In general, V(z) = STF(z)•U(z) + NTF(z)•E(z) simplest inputs, so treat the quantizer as an • For MOD1, NTF(z) = 1–z–1 additive noise source: The quantization noise has spectral shape! Y 4 π UVQ NTF()ej 2 f 2 3 -1 z E 2 ≅ ω2 for ω « 1 z-1 1 Y V V(z) = Y(z) + E(z) 0 0 0.1 0.2 0.3 0.4 0.5 Y(z) = ( U(z) – z-1V(z) ) / (1–z-1) Normalized Frequency (f /fs) ⇒(1–z-1) V(z) = U(z) – z-1V(z) + (1–z-1)E(z) • The total noise power increases, but the noise V(z) = U(z) + (1–z–1)E(z) power at low frequencies is reduced ECE1371 1-23 ECE1371 1-24 In-band Noise Power A Simulation of MOD1 σ2 • Assume that e is white with power e 0 ω σ2 ⁄ π Full-scale test tone i.e. See()= e • The in-band noise power is –20 SQNR = 55 dB @ OSR = 128 ω ω B B σ2 –40 N 2 = He()jω 2S ()ω dω ≅ ------e ω2dω 0 ∫ ee π ∫ Shaped “Noise” 0 0 –60 dBFS/NBW π π2σ2 ≡ 2 e ()–3 • SinceOSR ω------- , N 0 = ------------- OSR –80 20 dB/decade B 3 • For MOD1, an octave increase in OSR increases NBW = 5.7x10–6 SQNR by 9 dB –100 10–3 10–2 10–1 1.5-bit/octave SQNR-OSR trade-off. Normalized Frequency ECE1371 1-25 ECE1371 1-26 CT Implementation of MOD1 MOD1-CT Waveforms •Ri/Rf sets the full-scale; C is arbitrary u = 0 u = 0.06 Also observe that an input at fs is rejected by the 1 1 integrator— inherent anti-aliasing v v Integrator Latched –1 –1 Comparator C Rf y 0 y 0 Ri 0 5 10 15 20 0 5 10 15 20 u y D Q v Time Time DFF clock CK QB • With u=0, v alternates between +1 and –1 • With u>0, y drifts upwards; v contains consecutive +1s to counteract this drift ECE1371 1-27 ECE1371 1-28 Summary So Far MOD2: 2nd-Order ∆Σ Modulator • ∆Σ works by spectrally separating the • Replace the quantizer in MOD1 with another quantization noise from the signal copy of MOD1: • Noise-shaping is achieved by the use of filtering E1 and feedback E UVQ • A binary DAC is inherently linear, z-1 and thus a binary modulator is too z-1 z-1 –1 • MOD1 has NTF(z) = 1–z -1 ⇒ Arbitrary accuracy for DC inputs.