A Modular Soft Processor Core in VHDL Jack Whitham 2002-2003 This is a Third Year project submitted for the degree of MEng in the Department of Computer Science at the University of York. The project will attempt to demonstrate that a modular soft processor core can be designed and implemented on an FPGA, and that the core can be optimised to run a particular embedded application using a minimal amount of FPGA space. The word count of this project (as counted by the Unix wc command after detex was run on the LaTeX source) is 33647 words. This includes all text in the main report and Appendices A, B and C. Excluding source code, the project is 70 pages in length. i Contents I. Introduction 1 1. Background and Literature 1 1.1. Soft Processor Cores . 1 1.2. A Field Programmable Gate Array . 1 1.3. VHSIC Hardware Definition Language (VHDL) . 2 1.4. The Motorola 68020 . 2 II. High-level Project Decisions 3 2. Should the design be based on an existing one? 3 3. Which processor should the soft core be based upon? 3 4. Which processor should be chosen? 3 5. Restating the aims of the project in terms of the chosen processor 4 III. Modular Processor Design Decisions 4 6. Processor Design 4 6.1. Alternatives to a complete processor implementation . 4 6.2. A real processor . 5 6.3. Instruction Decoder and Control Logic . 5 6.4. Arithmetic and Logic Unit (ALU) . 7 6.5. Register File . 7 6.6. Links between Components . 8 7. The framework for a minimal processor 8 7.1. How this allows an application to be executed . 9 7.2. More complex features of the 68020 . 9 8. Compiling and testing 68020 programs 11 8.1. GCC Compilation Issues . 11 8.2. The Emulator . 12 9. What features can be modularised? 13 9.1. Modularisation of Instruction Support . 14 9.2. Modularisation of Registers . 14 9.3. Modularisation of ALU operations . 14 9.4. Modularisation of addressing modes . 14 9.5. Optimisation of the Addressing Width . 15 9.6. Writing the generator . 15 10.Designing processor components in VHDL 15 10.1. Control Logic . 16 10.2. Instruction Decoder . 19 10.3. Arithmetic and Logic Unit (ALU) . 21 ii 10.4. Register File . 21 10.5. Memory implementation . 22 10.6. Debugging Hardware . 23 10.7. Output Device . 24 11.The Generator 25 11.1. How should VHDL files be generated? . 25 11.2. Generator Directives . 26 11.3. Design of a 68020 program scanner . 26 12.Designing state machine sequences for instruction execution 27 IV. Implementation Phase 27 13.Implementing the fixed parts of the processor 27 13.1. The Control Logic . 28 13.2. The ALU . 29 13.3. The Register File . 32 13.4. The Memory Subsystem and Output Device . 32 13.5. Debugging Hardware Implementation . 34 14.Implementing control line sequences for 68020 instruction execution 36 14.1. Beginning to implement the 68020 instructions . 37 14.2. Defining the high level register transfers that are required . 37 14.3. Thinking at a lower level . 39 14.4. Implementing the Register Transfers in VHDL . 47 14.5. Implementing the state machine sequences for each instruction . 49 15.Implementing the generator 50 15.1. The state machine generator . 50 15.2. The instruction decoder generator . 52 15.3. The ALU and Effective Address optimisers . 57 15.4. The program scanner . 59 V. Evaluation and Conclusion 60 16.Evaluation 60 16.1. Does the State Machine Compiler work? . 60 16.2. Does the processor work? . 61 16.3. How much FPGA space does the processor take up? . 62 16.4. How does it compare to other soft processor cores? . 64 16.5. How extensible is the processor? . 65 16.6. Summary of the Evaluation . 65 17.Conclusion 65 VI. Appendices 66 A. Bibliography 66 iii B. Building-Block Hardware Components that appear in Diagrams 67 B.1. Multiplexers . 67 B.2. Links between Components . 68 B.3. Registers . 68 C. High-Level Register Transfers for Selected Instructions 68 D. Linker scripts and crt0.s 71 D.1. crt0.s file used for embedded applications . 71 D.2. tiny.x linker script used for the embedded applications . 72 E. VHDL sources 73 E.1. Source code of alu.vhd ......................................... 73 E.2. Source code of alu muxes.vhd ..................................... 75 E.3. Source code of alu segment.vhd .................................... 78 E.4. Source code of clock.vhd ........................................ 79 E.5. Source code of debugging.vhd ..................................... 80 E.6. Source code of do branch process.vhd ................................ 82 E.7. Source code of input.vhd ........................................ 82 E.8. Source code of memory.vhd ....................................... 83 E.9. Source code of operation size control process.vhd ........................ 86 E.10.Source code of register file.vhd ................................... 86 E.11.Source code of seven segment driver.vhd .............................. 88 E.12.Source code of state machine controller.vhd ........................... 89 E.13.Source code of types.vhd ........................................ 90 E.14.Source code of xilinx dp ram.vhd ................................... 90 F. Test Program sources 91 F.1. Source code of fib.c ........................................... 91 F.2. Source code of fvt.s ........................................... 91 F.3. Source code of 23instructions.s ................................... 95 G. State Machine Compiler sources 96 G.1. Source code of alu optimisation.cc ................................. 96 G.2. Source code of alu optimisation.h .................................. 96 G.3. Source code of control.cc ....................................... 96 G.4. Source code of control.h ........................................ 100 G.5. Source code of main.cc ......................................... 101 G.6. Source code of ndfa dag.cc ....................................... 102 G.7. Source code of ndfa dag.h ....................................... 105 G.8. Source code of ndfa node.cc ...................................... 105 G.9. Source code of ndfa node.h ....................................... 116 G.10.Source code of opcode map reader.cc ................................. 117 G.11.Source code of opcode map reader.h ................................. 121 G.12.Source code of optimisation.cc .................................... 122 G.13.Source code of optimisation.h .................................... 124 G.14.Source code of programram.cc ..................................... 126 G.15.Source code of programram.hh ..................................... 127 G.16.Source code of state.cc ......................................... 128 G.17.Source code of state.h ......................................... 131 G.18.Source code of state machine.cc ................................... 132 G.19.Source code of state machine.h .................................... 138 G.20.Source code of state machine loader.cc ............................... 139 iv G.21.Source code of state machine loader.h ............................... 142 G.22.Source code of utils.cc ......................................... 142 G.23.Source code of utils.h ......................................... 145 H. The Opcode Database 145 H.1. Source code of opcode map ....................................... 145 I. State Machine Sequences 147 I.1. Source code of alu a family.sm .................................... 147 I.2. Source code of alu a family cmp.sm .................................. 148 I.3. Source code of alu i cmp.sm ...................................... 149 I.4. Source code of alu i family.sm .................................... 150 I.5. Source code of alu no cmp.sm ...................................... 150 I.6. Source code of alu no family.sm .................................... 151 I.7. Source code of alu q family.sm .................................... 152 I.8. Source code of branch.sm ........................................ 152 I.9. Source code of clr.sm .......................................... 153 I.10. Source code of decbranch.sm ...................................... 154 I.11. Source code of decode ea.sm ...................................... 155 I.12. Source code of decode ea and dereference.sm ............................ 158 I.13. Source code of decode ea and store.sm ................................ 160 I.14. Source code of fetch extension dword.sm .............................. 161 I.15. Source code of fetch extension word.sm ............................... 162 I.16. Source code of fetch immediate data.sm ............................... 162 I.17. Source code of jmp.sm .......................................... 164 I.18. Source code of jsr.sm .......................................... 164 I.19. Source code of lea.sm .......................................... 165 I.20. Source code of link.sm ......................................... 166 I.21. Source code of move family.sm ..................................... 167 I.22. Source code of moveq.sm ......................................... 167 I.23. Source code of nop.sm .......................................... 168 I.24. Source code of pea.sm .......................................... 168 I.25. Source code of rts.sm .......................................... 169 I.26. Source code of scc.sm .......................................... 169 I.27. Source code of start.sm ......................................... 170 I.28. Source code of tst.sm .......................................... 171 I.29. Source code of unlk.sm ......................................... 172 v Part I. Introduction The aim of this project is to demonstrate that a modular soft processor core can be