VGA Registers (Sandybridge)

VGA Registers (Sandybridge)

Intel® OpenSource HD Graphics Programmer’s Reference Manual (PRM) Volume 3 Part 1: Display Registers – VGA Registers (SandyBridge) For the 2011 Intel Core Processor Family May 2011 Revision 1.0 NOTICE: This document contains information on products in the design phase of development, and Intel reserves the right to add or remove product features at any time, with or without changes to this open source documentation. Doc Ref #: IHD-OS-V3 Pt1 – 05 11 Creative Commons License You are free to Share — to copy, distribute, display, and perform the work Under the following conditions: Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any way that suggests that they endorse you or your use of the work). No Derivative Works. You may not alter, transform, or build upon this work. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The SandyBridge chipset family, Havendale/Auburndale chipset family, Intel® 965 Express Chipset Family, Intel® G35 Express Chipset, and Intel® 965GMx Chipset Mobile Family Graphics Controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel® sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel®. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2011, Intel Corporation. All rights reserved. 2 Doc Ref #: IHD-OS-V3 Pt1 – 05 11 Contents 1. VGA and Extended VGA Registers (00000h–00FFFh) ...................................................................... 5 1.1 General Control and Status Registers ................................................................................................. 6 1.1.1 ST00Input Status 0..................................................................................................................... 7 1.1.2 ST01Input Status 1..................................................................................................................... 8 1.1.3 FCRFeature Control ................................................................................................................... 9 1.1.4 MSRMiscellaneous Output ....................................................................................................... 10 1.2 Sequencer Registers.......................................................................................................................... 11 1.2.1 SRXSequencer Index ............................................................................................................... 12 1.2.2 SR00Sequencer Reset............................................................................................................. 13 1.2.3 SR01Clocking Mode................................................................................................................ 13 1.2.4 SR02Plane/Map Mask.............................................................................................................. 14 1.2.5 SR03Character Font.................................................................................................................15 1.2.6 SR04Memory Mode Register ................................................................................................... 16 1.2.7 SR07Horizontal Character Counter Reset ............................................................................... 17 1.3 Graphics Controller Registers............................................................................................................ 17 1.3.1 GRXGRX Graphics Controller Index Register.......................................................................... 17 1.3.2 GR00Set/Reset Register .......................................................................................................... 18 1.3.3 GR01Enable Set/Reset Register.............................................................................................. 18 1.3.4 GR02Color Compare Register ................................................................................................. 19 1.3.5 GR03Data Rotate Register....................................................................................................... 19 1.3.6 GR04Read Plane Select Register............................................................................................ 20 1.3.7 GR05Graphics Mode Register ................................................................................................. 21 1.3.8 GR06Miscellaneous Register................................................................................................... 23 1.3.9 GR07Color Don’t Care Register............................................................................................... 24 1.3.10 GR08Bit Mask Register .......................................................................................................... 25 1.3.11 GR10Address Mapping .......................................................................................................... 26 1.3.12 GR11Page Selector................................................................................................................ 28 1.3.13 GR18Software Flags .............................................................................................................. 28 1.4 Attribute Controller Registers............................................................................................................. 29 1.4.1 ARXAttribute Controller Index Register.................................................................................... 29 1.4.2 AR[00:0F]Palette Registers [0:F].............................................................................................. 30 1.4.3 AR10Mode Control Register..................................................................................................... 30 1.4.4 AR12Memory Plane Enable Register....................................................................................... 32 1.4.5 AR13Horizontal Pixel Panning Register................................................................................... 33 1.4.6 AR14Color Select Register....................................................................................................... 34 1.5 VGA Color Palette Registers ............................................................................................................. 34 1.5.1 DACMASKPixel Data Mask Register ....................................................................................... 35 1.5.2 DACSTATEDAC State Register............................................................................................... 36 1.5.3 DACRXPalette Read Index Register........................................................................................ 36 1.5.4 DACWXPalette Write Index Register ....................................................................................... 37 1.5.5 DACDATAPalette Data Register .............................................................................................. 37 1.6 CRT Controller Register..................................................................................................................... 38 1.6.1 CRXCRT Controller Index Register.......................................................................................... 39 1.6.2 CR00Horizontal Total Register................................................................................................. 40 1.6.3 CR01Horizontal Display Enable End Register ......................................................................... 40 1.6.4 CR02Horizontal Blanking Start Register .................................................................................. 41 1.6.5 CR03Horizontal Blanking End Register ................................................................................... 41 Doc Ref #: IHD-OS-V3 Pt1 – 05 11 3 1.6.6 CR04Horizontal Sync Start Register ........................................................................................ 42 1.6.7 CR05Horizontal Sync End Register ........................................................................................

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