SystemVerilog ● Industry's first unified HDVL (Hw Description and Verification language (IEEE 1800) ● Major extension of Verilog language (IEEE 1364) ● Targeted primarily at the chip implementation and verification flow ● Improve productivity in the design of large gate-count, IP- based, bus-intensive chips Sources and references 1. Accellera IEEE SystemVerilog page http://www.systemverilog.com/home.html 2. “Using SystemVerilog for FPGA design. A tutorial based on a simple bus system”, Doulos http://www.doulos.com/knowhow/sysverilog/FPGA/ 3. “SystemVerilog for Design groups”, Slides from Doulos training course 4. Various tutorials on SystemVerilog on Doulos website 5. “SystemVerilog for VHDL Users”, Tom Fitzpatrick, Synopsys Principal Technical Specialist, Date04 http://www.systemverilog.com/techpapers/date04_systemverilog.pdf 6. “SystemVerilog, a design and synthesis perspective”, K. Pieper, Synopsys R&D Manager, HDL Compilers 7. Wikipedia Extensions to Verilog ● Improvements for advanced design requirements – Data types – Higher abstraction (user defined types, struct, unions) – Interfaces ● Properties and assertions built in the language – Assertion Based Verification, Design for Verification ● New features for verification – Models and testbenches using object-oriented techniques (class) – Constrained random test generation – Transaction level modeling ● Direct Programming Interface with C/C++/SystemC – Link to system level simulations Data types: logic module counter (input logic clk, ● Nets and Variables reset, ● enable, Net type, Data type output logic q); ● Variables logic [7:0] count; ● Data type assign q = count[7]; ● New logic 4-state data always @(posedge clk or posedge type (synonym for reg) reset) begin ● Ports can be variables if (reset == 1'b1) count <= 0; ● Variables can be assigned else if (enable == 1'b1) in continuous statements count <= count + 1'b1; end ● Built-in: byte, shortint, endmodule: counter int, longint Packed and unpacked arrays logic [3:0][7:0] qBytes [0:15][1:3]; ● Multidimensional packed packed unpacked arrays unify and extend ... notion of registers and Qbytes[0][1][3][7] = 1'b1; memories unpacked packed Array querying functions logic [7:0] qBytes [0:15][1:3]; 3 1 2 $dimensions(qBytes) 3 $unpacked_dimensions(qBytes) 2 $left(qBytes) 0 $left(qBytes,2) 1 $right(qBytes,2) $right(qBytes,3) 3 0 $low(qBytes,2) $high(qBytes,2) 1 3 $size(qBytes,3) $size(qBytes,2) 8 3 $increment(qBytes,1) $bits(qBytes) -1 512 $increment(qBytes,3) 1 User defined types logic [3:0][7:0] qBytes [0:15][1:3]; ● User defined types with typedef typedef logic [7:0] octet_t; ● Higher level typedef octet_t [3:0] quadOctet_t; abstraction typedef qBytes_t quadOctet_t [0:15][1:3]; ● Design intent qBytes_t qBytes ; ... Qbytes[0][1] = 32'hFFFFFFF; Qbytes[0][1][2] = 8'hAA; Qbytes[0][2][3][7] = 1'b1; Enum SystemVerilog Struct tcp_t mypkt; … mypkt.source_port = 16'hAAAA; mypkt.dest_port = 16'hBBBB; 63 31 0 Design hierarchy module counter(input logic clk, reset, enable, output logic q); // … CODE HERE! endmodule: counter ● Creating a hierarchy in SystemVerilog is simpler (=less typing) than in module top(input logic clk, reset, enable, Verilog output logic RE, output logic WE, output types::addr_t addr, ● Use variables, no need of wires output types::rdata_t rdata, output types::wdata_t wdata); ● Implicit port connections logic en_data_gen, en_data_gen_b, q; Counter INST_C0(.clk, .reset, .enable, .q(en_data_gen)); Counter INST_C1(.*); // NOT RECOMMENDED! endmodule: top Packages package types; typedef logic [7:0] wdata_t; typedef struct packed { logic [3:0] data_h; logic [3:0] data_l; } wdata_struct_t; endpackage: types Allows sharing of: ● nets, variables, types, ● tasks, functions ● classes, extern constraints, extern methods ● parameters, localparams, spec params ● properties, sequences ● Unambiguous references to shared declarations • Built-in functions and types included in std package • Groups of files can be compiled separately Enabling efficient coding: example Channel INST_LEFT control INST_CTRL Channel INST_RIGHT Enabling efficient coding: example Channel INST_LEFT control INST_CTRL Channel INST_RIGHT Adding a signal can require editing through the full hierarchy module top(input logic clk, reset); logic [1:0] cfga, cfgb, cfgc, cfgd; control INST_CTRL(.clk(clk), .cfga(cfga), .cfgb(cfgb), .cfgc(cfgc), .cfgd(cfgd)); channel INST_LEFT(.clk(clk), .cfga(cfga[0]), .cfgb(cfgb[0]), .cfgc(cfgc[0]), .cfgd(cfgd[0])); channel INST_RIGHT(.clk(clk), .cfga(cfga[1]), .cfgb(cfgb[1]), .cfgc(cfgc[1]), .cfgd(cfgd[1])); endmodule : top SystemVerilog ports support struct types package types; typedef struct {logic cfga; module top(input logic clk); logic cfgb; logic cfgc; import types::*; logic cfgd; } configGroup_t; configGroup_t cfg [1:0]; endpackage: types control INST_CTRL(.clk, .cfg); module control(input logic clk, channel INST_LEFT(.clk, output types::configGroup_t cfg [1:0]); .cfg(cfg[0])); // … endmodule: control channel INST_RIGHT(.clk, .cfg(cfg[1])); module channel(input logic clk, input types::configGroup_t cfg); endmodule : top // … endmodule: channel Grouping signals and port with struc types enable avoiding editing through the full hierarchy Catch design intent: always_{comb,latch,ff} always_ff @(posedge clk or posedge reset) begin if (reset == 1'b1) count <= 0; else if (enable == 1'b1) count <= count + 1'b1; end Example basic design Interfaces are much more than sets of grouped variables (signals) ● SystemVerilog interface can have ports and contain variables and processes (like a module) ● It can connect to a module port (unlike a module) ● An interface that represents all of the wires within an on-chip bus only requires a single port connection to each master and slave on the bus ● modports within the interface allow master ports and slave ports to have different characteristics Conclusions on design extensions ● SystemVerilog raises abstraction level – Productivity improves – 3x to 5x code size reduction – Better and faster verification with synthesis ● Currently using Verilog for design? – clear advantages in updating to SystemVerilog – backwards compatible with all existing Verilog ● Currently using VHDL? – effort switching to SystemVerilog justified? If your designs contain on-chip multiplexed busses with multiple masters and slaves, it probably is ● Just starting out? – it makes sense to choose SystemVerilog as first design language to learn Extensions to Verilog ● Improvements for advanced design requirements – Data types – Higher abstraction (user defined types, struct, unions) – Interfaces ● Properties and assertions built in the language (SVA) – Assertion Based Verification, Design for Verification ● New features for verification – Models and testbenches using object-oriented techniques (class) – Transaction level modeling – Constrained random test generation ● Direct Programming Interface with C/C++/SystemC – Link to system level simulations ● Improvements for advanced design requirements – Data types – Higher abstraction (user defined types, struct, unions) – Interfaces ● New features for verification – Models and testbenches using object-oriented techniques (class) – Transaction level modeling – Constrained random test generation ● Properties and assertions built in the language – Assertion Based Verification, Design for Verification ● Direct Programming Interface with C/C++/SystemC – Link to system level simulations Assertions 0 1 2 3 4 5 6 read write req ack assert property ( @(posedge clk) read and write cannot be asserted simultaneously !(read && write) ); read or write cannot be asserted when req is not asserted assert property ( @(posedge clk) !((read || write) && !req) ); assert property ( @(posedge clk) ack must be active 1, 2 or 3 clock cycles after req req ##[1:3] ack ); assert property ( @(posedge clk) ack must change to active 1, 2 or 3 clock cycles after $rose(req) ##[1:3] $rose(ack)); req changes to active Sequences, properties, assertions property not_read_and_write; @(posedge clk) not (read && write); endproperty assert property (not_read_and_write); sequence request req; endsequence sequence acknowledge ##[1:3] Ack; endsequence property handshake; @(posedge clk) request |-> acknowledge; // property built from sequences and endproperty // implication operators |->, |=> assert property (handshake); // instruct simulator to react on verification cover property (handshake); // instruct simulator to count verification assert property ( !(read && write)read and); write cannot be asserted simultaneously or cannot be asserted when is not assert property ( !((read || write)read &&write !req) ); req asserted assert property ( @(posedge clk)ack must be active 1, 2 or 3 clock cycles after req req ##[1:3] ack ); assert property ( @(posedge clk)ack must change to active 1, 2 or 3 clock cycles after $rose(req) ##[1:3]req changes $rose to active(ack)); Binding to existing modules module MyDevice (...); // The design is modelled here endmodule ¼ program MyDevice_assertions(...); // sequences, properties, assertions for M go here endprogram ¼ bind MyDevice MyDevice_assertions INST_MYDEVICE_ASSERTIONS (...); Equivalent to: module MyDevice (...); // The design is modelled here program MyDevice_assertions(...); // sequences, properties, assertions for M go here Endprogram MyDevice_assertions INST_MYDEVICE_ASSERTIONS (...); endmodule property not_read_and_write; not (read && write); endproperty assert property (not_read_and_write); sequence request req; endsequence sequence acknowledge ##[1:2] Ack; endsequence property