Front cover ABCs of z/OS System Programming Volume 10 Alvaro Salla Patrick Oughton Redbooks International Technical Support Organization ABCs of z/OS System Programming Volume 10 May 2018 SG24-6990-05 Note: Before using this information and the product it supports, read the information in “Notices” on page vii. Sixth Edition (May 2018) This edition applies to version 2 release 3 of IBM z/OS (product number 5650-ZOS) and to all subsequent releases and modifications until otherwise indicated in new editions. © Copyright International Business Machines Corporation 2017, 2018. All rights reserved. Note to U.S. Government Users Restricted Rights -- Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Notices . vii Trademarks . viii Preface . ix The team who wrote this book . ix Now you can become a published author, too! . .x Comments welcome. .x Stay connected to IBM Redbooks . .x Chapter 1. Introduction to z/Architecture . 1 1.1 z/Architecture historical path . 2 1.2 Computer architecture overview . 3 1.3 Concept of a process . 5 1.4 System components . 7 1.4.1 System Assist Processor (SAP) . 8 1.4.2 Channels. 9 1.4.3 Dynamic Switch . 9 1.4.4 IBM Virtual Flash Memory (VFM) . 9 1.4.5 Pervasive encryption. 9 1.5 Processing units (PUs) . 10 1.6 Microcode Concepts . 11 1.7 z/Architecture Components. 12 1.8 PU Registers . 13 1.8.1 General purpose registers (GPR) . 14 1.8.2 Floating point registers . 15 1.9 Instruction set and its formats . 16 1.10 Program status word (PSW) . 17 1.10.1 PSW format. 18 1.11 Multiprocessing . 24 1.12 z/Architecture Data Formats . 24 1.12.1 Binary integers . 25 1.12.2 Decimal numbers . 25 1.12.3 Floating-point numbers . 26 1.12.4 EBCDIC data . 26 1.12.5 ASCII data. 27 1.12.6 Unicode. 27 1.12.7 UTF-8 . 27 1.13 IPL of a z/OS logical partition . 27 1.14 CPC memory addressing . 27 1.15 Addresses and address spaces . 28 1.16 Addressing mode . 30 1.16.1 AMODE. 30 1.16.2 RMODE. 31 1.17 Interrupts . 31 1.17.1 Reasons for interrupts. 33 1.17.2 Types of interrupts . 33 1.17.3 Interrupt processing . 37 1.18 Prefix Storage Area (PSA) . 38 1.19 Storage protection. 39 © Copyright IBM Corp. 2017, 2018. All rights reserved. iii 1.19.1 Storage key. 39 1.19.2 PSW key field . 40 1.19.3 Storage protection logic . 41 1.20 Virtual Storage initial concepts . 42 1.21 Segmenting a virtual address . 44 1.22 Dynamic address translation (DAT) (I) . 45 1.23 Dynamic Address Translation (DAT) (II) . 46 1.24 Translating large virtual address . 47 1.25 Page faults and page data sets. 49 1.26 A 64-bit Address Space . 51 1.27 Cross memory. 53 1.28 Access register mode (data spaces). 54 1.29 z/Architecture time facilities. 55 1.30 Server Time Protocol (STP) . 58 1.31 Hardware Configuration Definition (HCD) . 59 1.32 Logical channel subsystem (LCSS) . 61 1.33 Start Subchannel (SSCH) instruction logic . 62 1.34 I/O Interrupt processing. 66 1.35 DASD controllers (aka DASD controller ) . 67 1.36 Device number . ..