Nios II Classic Processor Reference Guide Subscribe NII5V1 101 Innovation Drive 2016.10.28 San Jose, CA 95134 Send Feedback www.altera.com TOC-2 Contents Introduction........................................................................................................ 1-1 Nios II Processor System Basics.................................................................................................................1-1 Getting Started with the Nios II Processor...............................................................................................1-2 Customizing Nios II Processor Designs....................................................................................................1-3 Configurable Soft Processor Core Concepts............................................................................................ 1-4 Configurable Soft Processor Core..................................................................................................1-4 Flexible Peripheral Set and Address Map..................................................................................... 1-4 Automated System Generation...................................................................................................... 1-5 Intel FPGA IP Evaluation ModeIntel FPGA IP Evaluation Mode........................................................ 1-5 Introduction Revision History................................................................................................................... 1-6 Processor Architecture........................................................................................ 2-1 Processor Implementation..........................................................................................................................2-2 Register File...................................................................................................................................................2-3 Arithmetic Logic Unit................................................................................................................................. 2-4 Unimplemented Instructions......................................................................................................... 2-4 Custom Instructions........................................................................................................................ 2-4 Reset and Debug Signals............................................................................................................................. 2-5 Exception and Interrupt Controllers......................................................................................................... 2-6 Exception Controller....................................................................................................................... 2-6 EIC Interface.....................................................................................................................................2-6 Internal Interrupt Controller..........................................................................................................2-7 Memory and I/O Organization..................................................................................................................2-7 Instruction and Data Buses.............................................................................................................2-8 Cache Memory............................................................................................................................... 2-10 Tightly-Coupled Memory.............................................................................................................2-11 Address Map................................................................................................................................... 2-12 Memory Management Unit.......................................................................................................... 2-12 Memory Protection Unit...............................................................................................................2-13 JTAG Debug Module................................................................................................................................. 2-13 JTAG Target Connection...............................................................................................................2-14 Download and Execute Software................................................................................................. 2-14 Software Breakpoints.....................................................................................................................2-14 Hardware Breakpoints...................................................................................................................2-14 Hardware Triggers..........................................................................................................................2-15 Trace Capture..................................................................................................................................2-16 Processor Architecture Revision History................................................................................................2-17 Programming Model........................................................................................... 3-1 Operating Modes..........................................................................................................................................3-1 Supervisor Mode.............................................................................................................................. 3-1 Altera Corporation TOC-3 User Mode.........................................................................................................................................3-2 Memory Management Unit........................................................................................................................ 3-2 Recommended Usage...................................................................................................................... 3-2 Memory Management..................................................................................................................... 3-3 Address Space and Memory Partitions......................................................................................... 3-4 TLB Organization............................................................................................................................ 3-5 TLB Lookups.....................................................................................................................................3-7 Memory Protection Unit.............................................................................................................................3-7 Memory Regions.............................................................................................................................. 3-8 Overlapping Regions....................................................................................................................... 3-9 Enabling the MPU............................................................................................................................3-9 Registers.........................................................................................................................................................3-9 General-Purpose Registers..............................................................................................................3-9 Control Registers............................................................................................................................3-10 Shadow Register Sets..................................................................................................................... 3-30 Working with the MPU.............................................................................................................................3-33 MPU Region Read and Write Operations.................................................................................. 3-33 MPU Initialization......................................................................................................................... 3-33 Debugger Access............................................................................................................................ 3-34 Working with ECC.....................................................................................................................................3-34 Enabling ECC................................................................................................................................. 3-34 Handling ECC Errors.................................................................................................................... 3-34 Injecting ECC Errors..................................................................................................................... 3-35 Exception Processing.................................................................................................................................3-36 Terminology....................................................................................................................................3-36 Exception Overview.......................................................................................................................3-37 Exception Latency..........................................................................................................................3-39 Reset Exceptions.............................................................................................................................3-40