Using High-Speed ® I/O Standards in APEX II Devices May 2003, ver. 1.8 Application Note 166 Introduction Recent expansion in the telecommunications market and growth in Internet use have created a demand to move more data faster than ever. To meet this demand, system designers are relying on solutions such as differential signaling and interface standards such as RapidIO, POS-PHY Level 4, or UTOPIA IV. The APEXTM II device’s high-speed interface I/O pins offer serialization and deserialization on a single chip to move data at high speeds. They also utilize a state-of-the-art CMOS process that consumes far less power than GaAs devices, the other alternative for high-speed devices. Preliminary The following documents are available and provide information on Information APEX II device high speed I/O standard features and functions. These documents also explain how system designers can take advantage of these standards to increase system efficiencies and bandwidth. ■ Application Note 157 (Using CDS in APEX II Devices) describes the most common topologies, and how the APEX II device’s unique clock-data synchronization (CDS) feature is applied. ■ Application Note 167 (Using Flexible-LVDS in APEX II Devices) describes the function, capabilities, and implementation of the Flexible-LVDSTM buffer. The APEX II high-speed interface includes four I/O banks. Each high- speed I/O bank is comprised of 18 channels, offering 36 differential input and 36 differential output channels each running up to 1 gigabit per second (Gbps). The 72 channels combine to offer 366-Gbps throughput. See Figure 1. APEX II devices combine serialization, deserialization, and frequency multiplication into one package. This combination allows APEX II devices to transmit multiple bits of data through a reduced number of differential transmission lines spanning large distances. Altera Corporation 1 AN-166-1.8 AN 166: Using High-Speed I/O Standards in APEX II Devices Preliminary Information Figure 1. APEX II High-Speed Interface Block Diagram I/O Bank I/O Bank Receiver Transmitter Input Clock 1 Output Clock 1 PLL1 PLL1 True-LVDS True-LVDS Channels 1 to 18 Channels 1 to 18 Serial Data Serial Data Serial-to-Parallel Parallel-to-Serial Converter Converter System I/O BankLogic I/O Bank True-LVDS True-LVDS Channels 19 to 36 Channels 19 to 36 Serial Data Serial Data Serial-to-Parallel Parallel-to-Serial Converter Converter Input Clock 2 Receiver Transmitter Output Clock 2 PLL2 PLL2 APEX II High- As demand for high-speed systems grows, the interface between systems becomes critical. The APEX II high-speed interface offers four types of Speed I/O commonly applied high-speed I/O standards: LVDS, HyperTransport, Standards LVPECL, and PCML. Figures 2 and 3 show receiver input and transmitter output waveforms, respectively, for all differential I/O standards (LVDS, 3.3-V PCML, LVPECL, and HyperTransport technology). 2 Altera Corporation Preliminary Information AN 166: Using High-Speed I/O Standards in APEX II Devices Figure 2. Receiver Input Waveforms for Differential I/O Standards Single-Ended Waveform Positive Channel (p) = VIH ±VID Negative Channel (n) = VIL VCM Ground Differential Waveform +VID p − n = 0 V V − ID (Peak-to-Peak) VID Figure 3. Transmitter Output Waveforms for Differential I/O Standards Single-Ended Waveform Positive Channel (p) = VOH ±VOD Negative Channel (n) = VOL VCM Ground Differential Waveform +VOD p − n = 0 V V (1) − SS VOD Note to Figure 3: (1) VSS: steady-state differential output voltage. LVDS LVDS is a low-voltage differential signaling, general-purpose I/O standard. This I/O standard can transmit signals at high data rates across a variety of interconnect media such as printed circuit board (PCB) traces, backplanes, or cables with minimal power consumption and low noise. Altera Corporation 3 AN 166: Using High-Speed I/O Standards in APEX II Devices Preliminary Information APEX II device True-LVDSTM buffers (see Figure 4) meet complex design requirements for high data rates and low power consumption by using a low-voltage differential signal that can travel at rates up to 1 Gbps. Two key industry standards define LVDS: IEEE Std. 1596.3 SCI-LVDS and ANSI/TIA/EIA-644. Although both standards have similar features, the IEEE Std. 1596.3 SCI-LVDS standard supports a maximum data transfer rate of only 250 megabits per second (Mbps). APEX II devices are designed to meet the ANSI/TIA/EIA-644 standard while supporting a maximum data transfer rate of 1 Gbps. Table 1 lists the LVDS parameters. Figure 4. LVDS Buffers Driver Current Source ~3.5 mA Receiver – + 100 + – 4 Altera Corporation Preliminary Information AN 166: Using High-Speed I/O Standards in APEX II Devices Table 1. 3.3-V LVDS Specifications Note (1) Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO I/O supply voltage 3.135 3.3 3.465 V VOD Differential output voltage RL = 100 Ω 250 850 (2) mV ∆ VOD Change in VOD between RL = 100 Ω 50 mV high and low VOS Output offset voltage RL = 100 Ω 1.125 1.25 1.375 V ∆ VOS Change in VOS between RL = 100 Ω 50 mV high and low VTH Differential input threshold VCM = 1.2 V –100 100 mV VIN Receiver input voltage 0.0 2.4 V range RL Receiver differential input 90 100 110 Ω resistor (external to APEX II devices) Notes to Table 1: (1) APEX II devices support the RapidIO and POS-PHY Level 4 interconnect standards using the LVDS I/O standard. (2) Maximum VOD is measured under static conditions. HyperTransport HyperTransport (formerly known as Lightning Data Transport, or LDT) technology is a new high-speed, high-performance point-to-point I/O standard for connecting integrated circuits on a motherboard. It is primarily targeted for the IT and telecommunication industries, but any application that requires high speed, low latency, and scalability has the potential to take advantage of HyperTransport technology. HyperTransport technology connections have two unidirectional point- to-point links with varied bit widths, and the clock is center-aligned with data. The APEX II transmitter circuitry allows users to select edge-aligned or center-aligned strobe method for each individual channel, regardless of the I/O standard used. Table 2 lists the HyperTransport parameters. Altera Corporation 5 AN 166: Using High-Speed I/O Standards in APEX II Devices Preliminary Information Table 2. HyperTransport Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO I/O supply voltage 2.375 2.5 2.625 V VOD Differential output voltage RL = 100 Ω 380 600 820 mV VOCM Output common mode RL = 100 Ω 500 600 700 mV voltage VID Differential input voltage 300 600 900 mV VICM Input common mode 450 600 750 mV voltage RL Receiver differential input 90 100 110 Ω resistor LVPECL The LVPECL I/O standard is used in telecommunications, data communications, and clock distribution fields. It uses a positive power supply, and has relatively small voltage swing compared to TTL I/O standards, making LVPECL suitable for high-speed systems. Table 3 shows the LVPECL signaling characteristics. Table 3. LVPECL Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO I/O supply voltage 3.135 3.3 3.465 V VIL Low-level input voltage 800 1,700 mV VIH High-level input voltage 2,100 VCCIO mV VOL Low-level output voltage 1,450 1,650 mV VOH High-level output voltage 2,275 2,420 mV VID Differential input voltage 100 600 2,500 mV VOD Differential output voltage 625 800 970 mV tR Rise time (20 to 80%) 85 325 ps tF Fall time (20 to 80%) 85 325 ps 6 Altera Corporation Preliminary Information AN 166: Using High-Speed I/O Standards in APEX II Devices PCML The PCML buffers provide programmable, differential current outputs into transmission lines with 50-Ω terminations. The PCML I/O buffer features 3.3-V operation and, similar to LVDS, consumes less power than PECL. PCML signaling characteristics of are shown in Table 4. Table 4. PCML Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO I/O supply voltage 3.135 3.3 3.465 V VIL Low-level input voltage VCCIO – V 0.3 VIH High-level input voltage VCCIO V VOL Low-level output voltage VCCIO – VCCIO – V 0.6 0.3 VOH High-level output voltage VCCIO – VCCIO V 0.3 VT Output termination voltage VCCIO V VOD Differential output voltage 300 450 600 mV tR Rise time (20 to 80%) 85 325 ps tF Fall time (20 to 80%) 85 325 ps RO Output load 100 Ω RL Receiver differential input 45 50 55 Ω resistor APEX II High- The APEX II device’s high-speed interface combines serialization, frequency multiplication, and deserialization all in one circuit. This allows Speed Interface APEX II devices to transmit many bits of data through a reduced number Technology of differential transmission lines over distances greater than those that can be achieved with a single-ended (e.g., TTL or CMOS) interface. The designer can select the number of bits combined or multiplexed per transmission link, resulting in a more flexible interface than with the fixed-ratio solutions of application-specific integrated circuit (ASIC) or application-specific standard product (ASSP) devices. A designer using an ASIC or ASSP device must use a fixed number of high-speed channels as well as a fixed number of serialized bits per channel. These limitations reduce efficiency and flexibility, increase die size, and inflate the cost of the system. In contrast, APEX II devices allow designers to select the number of high-speed channels used and determine the best use of system resources.