Analog VLSI Circuit Design: Linear Voltage Regulator Instructor: Professor Prodanov California Polytechnic State University Spring 2016 Written By: Brett Colteaux Kirstie Fung i Abstract The project outlined in this report is the design, layout, and routing of a linear voltage regulator using Cadence VLSI (very-large-scale integration) software. The design specifications for this regulator are as follows: input voltage range of 5V + 1V, load current capabilities of 150mA, and output voltage range of 1.15V to 3.3V. Furthermore, the design of this circuit was broken into three main sub-circuits: an error amplifier, bandgap reference circuitry, and biasing circuitry for the bandgap. Together, these sub-circuits integrated to make the final design. Research for different topologies for a voltage regulator was done and the Brokaw bandgap reference circuit by Paul Brokaw was used for the reference voltage. The layout and routing of these sub-circuits was performed by breaking these sub-circuits into even smaller sub-circuits and routing these individually. In the end, the group was able to layout and route all of the sub-circuits. However, several DRC and LVS errors were encountered throughout the layout process. Main sources of errors were due to the bipolar junction transistors and resistors used in this design. To the best knowledge of the group, layout and routing of the bipolar junction transistors used in this design have never been attempted at California Polytechnic State University San Luis Obispo. Therefore, it was expected that the group ran into several problems with these devices and it is outlined in the report how some of these problems were resolved. From the final design, it was found that the voltage regulator that was created in Cadence has an output voltage of about 3.4V; 100mV more than the intended 3.3V, yielding a discrepancy of 3% from the design specifications. In regards to temperature, the design deviates about 85mV across the industrial temperature range of -40 to 100. Another metric that was used to test the final design is the voltage deviation when the load current is swept from 0-150mA,which was found to be 170mV. It was found that the subcircuits created for this project performed fairly close to the intended purpose and therefore the design of the voltage regulator is seen as a success. Thus, the next step for this project will be to fix the DRC and LVS errors associated with BJTs and resistors. After that, extraction of the circuit should be done to determine the parasitic capacitance and inductance associated with this circuit. And finally, the GDSII file should be made to be sent to the chip manufacturer to tape-out the chip. ii Table of Contents Introduction ..................................................................................................................................... 1 Design ............................................................................................................................................. 4 DRC .............................................................................................................................................. 47 LVS ............................................................................................................................................... 50 Next Steps ..................................................................................................................................... 53 Conclusion .................................................................................................................................... 53 Appendix ....................................................................................................................................... 55 References ..................................................................................................................................... 57 iii List of Figures Figure 1: Linear Voltage Regulator Block Diagram ..................................................................... 2 Figure 2: Typical Linear Regulator Schematic .............................................................................. 3 Figure 3: Texas Instrument’s LM317-N Block Diagram [7]. ........................................................ 3 Figure 4: Reference Voltage Created Via PTAT and CTAT. ........................................................ 5 Figure 5: Brokaw Bandgap Reference Circuitry ........................................................................... 5 Figure 6: Schematic Used to Characterize VNPN BJT. ................................................................ 7 Figure 7: Characterization of VNPN Bipolar Junction Transistor. ............................................... 8 Figure 8: Schematic Used to Characterize VPNP BJT. ................................................................. 9 Figure 9: Characterization of VPNP Bipolar Junction Transistor. ............................................. 10 Figure 10: Schematic Used to Characterize PFETX MOSFET. .................................................. 11 Figure 11: Brokaw Bandgap Circuit using Cadence PCells ........................................................ 12 Figure 12: Reference Voltage Output of the Brokaw Bandgap ................................................... 13 Figure 13: Zoomed in Reference Voltage Output of the Brokaw Bandgap ................................ 13 Figure 14: Bandgap Reference with Simple PMOS Current Mirror. .......................................... 14 Figure 15: Simple PMOS Current Mirror. ................................................................................... 15 Figure 16: Currents in the Simple PMOS Current Mirror. .......................................................... 15 Figure 17: Currents in the Simple PMOS Current Mirror with M=3. ......................................... 16 Figure 18: Bandgap Reference with Cascaded PMOS Current Mirror. ...................................... 17 Figure 19: Cascoded PMOS Current Mirror. ............................................................................... 17 Figure 20: Currents in the Cascoded PMOS Current Mirror. ...................................................... 18 Figure 21: Prodanov Current Mirror Schematic. ......................................................................... 19 Figure 22: Prodanov Current Mirror Simulation. ........................................................................ 20 Figure 23: Bandgap Reference Circuitry with Prodanov Current Mirror. ................................... 21 Figure 24: Currents in the Prodanov Current Mirror. ................................................................. 22 Figure 25: Optimized Output Voltage of Bandgap Reference Across Temperature. .................. 22 Figure 26: Transient Response of Bandgap Reference at 25℃. .................................................. 23 Figure 27: Error Amplifier Schematic. ........................................................................................ 24 Figure 28: Simulated Transient Response of V+ and V- nodes of op amp. ................................ 25 Figure 29: Output Voltage of Regulator from Error Amplifier Circuit. ...................................... 26 Figure 30: Simulated Output Voltage of Error Amplifier Circuit as Load Swept. ...................... 26 Figure 31: Positive and Negative Terminals of Error Amplifier as Load Swept. ....................... 27 Figure 32: Final Schematic of Regulator Design ......................................................................... 27 Figure 33: Final Schematic of Regulator Design Used for Simulating. ...................................... 28 Figure 34: Output Voltage Transient Response. .......................................................................... 29 Figure 35: Output Voltage Across Temperature for a Load of 75mA and Temperature 25℃. ... 29 Figure 36: Output Voltage Across Load Current Sweep of 150mA. ........................................... 30 Figure 37: Current Mirror at 75mA Load Current and T=25℃. .................................................. 30 Figure 38: Current Mirror Temperature Sweep. .......................................................................... 31 Page 2 Figure 39: Current Mirror Performance Across Load Current Sweep. ....................................... 31 Figure 40: Transient Response of Error Amplifier Terminals ..................................................... 32 Figure 41: Temperature Sweep of Error Amplifier Terminals .................................................... 32 Figure 42: Load Current Sweep of Error Amplifier Terminals ................................................... 33 Figure 43: Output Voltage over 5V Supply Voltage Sweep ....................................................... 33 Figure 44: Output Voltage over 5V to 3.28V Supply Voltage Sweep. ....................................... 34 Figure 45: Bandgap Voltage Transient Response ........................................................................ 34 Figure 46: Bandgap Voltage Across Temperature Sweep. .......................................................... 35 Figure 47: Bandgap Voltage Across Load Current Sweep .......................................................... 35 Figure 48: Ten Transistor Schematic for Power Transistor. ........................................................ 36 Figure 49: Ten Transistor Layout for Power Transistor. ............................................................. 37 Figure 50: Error Amplifier Schematic Without