Intel® Quartus® Prime Pro Edition User Guide Getting Started Updated for Intel® Quartus® Prime Design Suite: 21.2 Subscribe UG-20129 | 2021.06.21 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction to Intel® Quartus® Prime Pro Edition......................................................... 5 1.1. Selecting an Intel Quartus Prime Software Edition......................................................6 1.2. Introduction to Intel Quartus Prime Pro Edition Revision History...................................8 2. Managing Intel Quartus Prime Projects........................................................................ 10 2.1. Viewing Basic Project Information.......................................................................... 11 2.1.1. Using the Compilation Dashboard...............................................................12 2.1.2. Viewing Project Reports............................................................................ 13 2.1.3. Viewing Project Messages......................................................................... 14 2.1.4. Automated Problem Reports...................................................................... 17 2.2. Intel Quartus Prime Project Contents......................................................................17 2.2.1. Project File Best Practices..........................................................................18 2.3. Managing Project Settings.....................................................................................18 2.3.1. Specifying the Target Device or Board.........................................................19 2.3.2. Optimizing Project Settings....................................................................... 20 2.4. Managing Logic Design Files.................................................................................. 24 2.4.1. Including Design Libraries......................................................................... 25 2.4.2. Creating a Project Copy............................................................................ 25 2.5. Managing Timing Constraints.................................................................................25 2.6. Integrating Other EDA Tools.................................................................................. 26 2.7. Exporting Compilation Results............................................................................... 27 2.7.1. Exporting a Version-Compatible Compilation Database ................................. 28 2.7.2. Importing a Version-Compatible Compilation Database .................................29 2.7.3. Creating a Design Partition........................................................................30 2.7.4. Exporting a Design Partition...................................................................... 32 2.7.5. Reusing a Design Partition.........................................................................34 2.7.6. Viewing Quartus Database File Information................................................. 35 2.7.7. Clearing Compilation Results..................................................................... 37 2.8. Migrating Projects Across Operating Systems...........................................................38 2.8.1. Migrating Design Files and Libraries............................................................38 2.8.2. Design Library Migration Guidelines............................................................ 39 2.9. Archiving Projects................................................................................................ 39 2.9.1. Manually Adding Files To Archives.............................................................. 40 2.9.2. Archiving Projects for Service Requests.......................................................40 2.9.3. Archiving Projects for External Revision Control............................................41 2.9.4. Creating Database-Only Archives............................................................... 42 2.10. Command-Line Interface.....................................................................................43 2.10.1. Project Revision Commands.....................................................................44 2.10.2. Project Archive Commands...................................................................... 44 2.10.3. Project Database Commands................................................................... 45 2.11. Managing Projects Revision History.......................................................................46 3. Design Planning............................................................................................................ 49 3.1. Design Planning...................................................................................................49 3.2. Create a Design Specification and Test Plan............................................................. 49 3.3. Plan for the Target Device..................................................................................... 49 3.3.1. Device Migration Planning......................................................................... 51 3.4. Plan for Intellectual Property Cores........................................................................ 51 Intel Quartus Prime Pro Edition User Guide: Getting Started Send Feedback 2 Contents 3.5. Plan for Standard Interfaces..................................................................................52 3.6. Plan for Device Programming.................................................................................52 3.7. Plan for Device Power Consumption........................................................................53 3.8. Plan for Interface I/O Pins.....................................................................................55 3.8.1. Simultaneous Switching Noise Analysis....................................................... 57 3.9. Plan for other EDA Tools....................................................................................... 58 3.9.1. Third-Party Synthesis Tools....................................................................... 58 3.9.2. Third-Party Simulation Tools...................................................................... 58 3.10. Plan for On-Chip Debugging Tools.........................................................................58 3.11. Plan HDL Coding Styles.......................................................................................59 3.11.1. Design Recommendations........................................................................60 3.11.2. Recommended HDL Coding Styles............................................................ 60 3.11.3. Managing Metastability........................................................................... 60 3.12. Plan for Hierarchical and Team-Based Designs........................................................61 3.12.1. Flat Compilation without Design Partitions................................................. 61 3.13. Design Planning Revision History..........................................................................61 4. Introduction to Intel FPGA IP Cores..............................................................................65 4.1. IP Catalog and Parameter Editor............................................................................ 66 4.1.1. The Parameter Editor................................................................................67 4.2. Installing and Licensing Intel FPGA IP Cores............................................................ 67 4.2.1. Intel FPGA IP Evaluation Mode................................................................... 68 4.3. IP General Settings.............................................................................................. 71 4.4. Adding IP to IP Catalog.........................................................................................72 4.5. Best Practices for Intel FPGA IP..............................................................................73 4.6. Specifying the IP Core Parameters and Options (Intel Quartus Prime Pro Edition)......... 74 4.6.1. IP Core Generation Output (Intel Quartus Prime Pro Edition)..........................76 4.6.2. Scripting IP Core Generation..................................................................... 78 4.7. Modifying an IP Variation...................................................................................... 78 4.8. Upgrading IP Cores.............................................................................................. 78 4.8.1. Upgrading IP Cores at Command-Line.........................................................81 4.8.2. Migrating IP Cores to a Different Device...................................................... 82 4.8.3. Troubleshooting IP or Platform Designer System Upgrade.............................. 83 4.9. Simulating Intel FPGA IP Cores.............................................................................. 84 4.9.1. Generating IP Simulation Files................................................................... 84 4.9.2. Scripting IP Simulation............................................................................. 85 4.10. Simulating Platform Designer Systems.................................................................. 94 4.11. Synthesizing IP Cores in Other EDA Tools.............................................................. 96 4.12. Instantiating IP Cores in HDL...............................................................................97