Silicon spin qubits LETI INNOVATION DAYS 2019 S. De Franceschi2, L. Hutin1, B. Bertrand1, S. Barraud1, J.-M. Hartmann1, Y.-J. Kim1, V. Mazzocchi1, A. Amisse1,2, H. Bohuslavskyi1,2, L. Bourdet2, A. Crippa2, X. Jehl2, R. Maurand2, R. Ezzouch2, A. Aprà2, Y.-M. Niquet2, M. Sanquer2, B. Venitucci2, L. Le Guevel1,2, G. Pillonnet1, G. Billot1, B. Jadot3, E. Chanrion3, C. Spence3, D.J. Niegemann3, B. Klemt3, P.-A. Mortemousque3, M. Urdampilleta3, and T. Meunier3, M. Vinet1 1Univ. Grenoble Alpes, CEA, LETI, Minatec Campus, F-38000 Grenoble, France 2Univ. Grenoble Alpes, CEA, IRIG, PHELIQS, F-38000 Grenoble, France 3Univ. Grenoble Alpes, CNRS, Institut Néel, F-38000 Grenoble, France 1 From the first transistor to VLSI: 70 years of development 1947: First transistor 1958: First integrated circuit 1959: First silicon IC (Robert Noyce) (Bardeen, Schockley & 1968: Intel 4004 (Federico Faggin) Brattain, Nobel 1956) (Jack Kilby, Nobel 2000) Long spin coherence in isotopically purified silicon Science 2012 Spin qubit 31P Nat. Mater. 2011 3 Semiconductor spin qubits Quantum information encoded in a spin d = |g mB B| degree of freedom Nuclear spin of Spin of an a donor atom electrostatically confined electron Kane, Nature (1998) Loss & DiVincenzo, PRA (1998) 4 First electron spin qubit in a natural-Si MOS device Dzurak/Morello group (UNSW, Sydney) Pla et al., Nature (2012) 5 6 Si spin qubits: late but quickly rising J. Yoneda et al. (RIKEN) Takeda et al. (RIKEN) D. Zajac et al. (Princeton) M. Veldhorst et al. (UNSW) R. Maurand et al. (CEA) E. Kawakami et al. (TUDelft) J. Pla et al. (UNSW) Material engineering (isotopic purification, charge noise reduction…) Improved control schemes (e.g. electric-field driven spin manipulation) => Higher # of ”operations per error” Two-qubit quantum gates: tunnel mediated exchange Princeton (2018) UNSW (2018) Delft/Wisconsin (2018) State-of-the-art: 98% two-qubit gate fidelity (UNSW) 7 Si spin qubits: current state-of-the-art Long spin coherence thanks to isotopic purification One- and two-qubit gates demonstrated Still room for improving fidelities LARGE SCALE QUBIT INTEGRATION 8 9 Physics-Engineering Synergy www.quantumsilicon-grenoble.eu 8000 m2 cleanroom y 10 Silicon nanowire MOSFET Transversal cross-section Si Top view 10 nm G Longitudinal cross-section S D 100 nm From MOSFETs to MOS-SETs 20nm 10nm LG FET 20nm=7.8nm SET5nm TSi G =7nm TSiO2 VG VG a-Si LG V 3.4nm VS D VS VD S D 7nm SiO2 BOX SiO2 VG=0 VG>0 A single electron tunnels and gets trapped in the quantum dot 11 Few-hole quantum dot in Silicon-On-Insulator VG < undoped channel 0 p-type leads Ev gate drain -5 10 300K 300mK -6 source 10 Lg ~ 25 nm -7 10 G (S) -8 15 nm 10 VT -9 Si 10 11 11 nm -700 -600 -500 -400 -300 -200 Gate voltage (mV) First Coulomb-blockade peaks lie in the ‘overthreshold’ regime 12 Few-hole quantum dot in Silicon-Onb-Insulator H Li Spin-1/2 quantum dot: Nano Lett., 2016, 16 (1), pp 88–92 ۧ↑ȁ EZ = |g.µB.B| ۧ↓ȁ 13 First silicon CMOS spin qubit VG1 < 0 VG2 < 0 Based on hole spin, exploting spin-orbit coupling Ev in the silicon valence band Rabi frequency up to 80 MHz spin qubit readout spin Exp: Maurand et al., Nat. Comm. 2016 Exp: Crippa et al., Phys. Rev. Lett. 2018 Th: Venitucci et al., arXiv:1807.09185 Hutin et al., VLSI 2016 14 More recent data… RABI -3.60 burst -3.70 -3.80 -12 Current (A) -3.90x10 0 100 200 300 400 (nS) burst (ns) Burst RAMSEY T2* ~ 270 ns Free evolution 휏 -2.85 -2.90 -2.95 -3.00 Current (A) -12 -3.05x10 -9 0 100 200 300 400x10 (nS) 휏Burst(ns) Hutin, et al., ESSDERC 2018 15 High-Fidelity Electron-Spin Readout via RF Gate Reflectometry Fidelity > 99% ۧ↓ȁ↑ۧ ȁ Urdampilleta et al., Nature Nano 2019 40 nm (also Crippa et al. Nat. Comm., in press) 16 Outlook S D « perturbative » approach: Fast prototyping - obvious CMOS-compatibility Limited qubit interconnectivity New paradigm: Compatible with surface-code QC 3D integration to develop QuCube 17 18 www.quantumsilicon-grenoble.eu.