Processor Architectures for Synthetic Aperture Radar by Peter G. Meisl B.A.Sc. Electrical Engineering, University of British Columbia, 1990 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES DEPARTMENT OF ELECTRICAL ENGINEERING We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA March 1996 © Peter Meisl, 1996 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of f3 leciy* c»\ E>n^ t n^e/i The University of British Columbia Vancouver, Canada Date DE-6 (2/88) -l : Abstract This thesis examines processor architectures for Synthetic Aperture Radar (SAR). SAR is a remote sensing technique that requires large amounts of computation and memory to form images. Processor architectures are sought that exhibit high performance, are scalable, are flexible, and are cost effective to develop and build. Performance is taken to be the primary figure of merit. The three facets of systems design, namely algorithm, technology, and architecture, are each examined in the process of finding the best architecture implementations. The examination of the algorithms is begun by reviewing SAR processing theory with the intent of summarizing the background for typical SAR proc• essor performance requirements. A representative set of SAR algorithms is analyzed to determine and compare their computational requirements and to characterize them in terms of basic digital signal processing (DSP) operation types.,The algorithm partitioning options for parallel processing are classified and compared. The area of technology is addressed by surveying computing technologies that are relevant to SAR processing. The technologies considered cover computational devices, memory devices and interconnec• tions. The knowledge of SAR algorithms and computing technology are then combined to study design consider• ations for the memory and interconnection subsystems of SAR processors. The requirement for two dimensional access to large data arrays is found to be the main complicating factor in memory design. The judicious use of wide data path widths, caches, interleaving and fast memory is discussed as a solution to the memory latency problem. The applicability of the most commonly used interconnection networks is examined. Buses, meshes, and crossbars are all found to be effective in certain situations. A classification of architectural approaches adapted to describe current and future SAR processors is used as the framework for the architecture selection. Feasible implementations of the architectural approaches are identified and their suitability for SAR is analyzed. Three approaches are identified as the most promis• ing: networks of workstations, DSP chips, and field programmable gate arrays (FPGAs). A detailed exam• ination is made of these three approaches. Four variations of the DSP approach are considered: general purpose DSPs, vector DSPs, a proposed optimised DSP, and digital filter devices. Each approach offers a different trade-off between performance and flexibility. The most cost effective architectures approaches are found to be those based on general purpose or vector DSPs. An original heterogeneous design is pre• sented that combines the strengths of these two approaches. ii Table of Contents Abstract ii Table of Contents iii List of Tables vi List of Figures vii Symbols and Acronyms ix Acknowledgment xiii 1 Introduction 1 1.1 Background 1 1.2 Objectives 2 1.3 Outline 2 2 Overview of SAR Processing 4 2.1 SAR Processing Requirements 4 2.1.1 General SAR Background 4 2.1.2 Azimuth Frequency 7 2.1.3 Resolution • 8 2.1.4 Range Cell Migration 9 2.1.5 Correlation Processing 10 2.1.6 Data Set Sizes 12 2.1.7 Summary 14 2.2 SAR Sensors 14 2.3 SAR Processors 16 2.4 Common SAR Algorithms 17 2.4.1 Time Domain Algorithm 19 2.4.2 SPECAN Algorithm 19 2.4.3 Range-Doppler Algorithm 21 2.4.4 Two Dimensional Frequency Domain Algorithms 22 2.4.5 Chirp Scaling Algorithm 23 2.4.6 Algorithm Variations 24 2.5 Computational Analysis of SAR Algorithms 25 2.5.1 Operation Types 25 2.5.2 Computational Requirements of SAR Algorithms 26 2.5.3 Model of Post-Processing Operations 36 2.5.4 Model of Range-Doppler Algorithm 38 2.6 Partitioning of SAR Processing 40 2.6.1 Considerations for Parallelism 41 2.6.2 Granularity of Parallelism 42 2.6.3 Classification of Approaches to Partitioning 43 2.6.4 An Example of Horizontal Data Partitioning: Range-Doppler Algorithm .........47 3 SAR Processor System Design 49 3.1 Design Methodology 49 3.2 System Requirements 50 3.3 System Design Considerations 51 3.4 Performance Prediction ; 52 iii 3.5 Architecture Selection Criteria 53 4 Architectural Approaches 55 4.1 Single Processor 55 4.2 Common Node Processor 55 4.3 Multiprocessor 57 4.4 Pipeline Processor 58 4.5 Multicomputer 59 4.6 SIMD Processor 60 4.7 Hardwired 61 5 Computing Technology 62 5.1 General Purpose Microprocessors 62 5.2 General Purpose DSPs 64 5.3 Special Purpose DSPs 65 5.3.1 Accelerated FFT Chips 66 5.3.2 Digital Filter Chips 67 5.4 Custom and Semi-Custom VLSI 67 5.5 Field Programmable Logic 68 5.6 Memory 68 5.7 Interconnect 70 6 Architecture Implementation Alternatives 73 6.1 Workstation 73 6.2 Accelerated General Purpose Computer 74 6.3 Supercomputer 75 6.4 Network of Workstations 75 6.5 DSP Uniprocessor and Multicomputer 77 6.6 Reconfigurable Computing Machine 78 6.7 Custom Algorithm Specific Processor 79 7 Memory System Design 81 7.1 High Performance Data Path Design 81 7.2 Memory Access in SAR Processing 82 7.3 Corner turns 82 7.3.1 Singe Processor Corner Turns 82 7.3.2 Multiple Processor Corner Turns 83 7.4 Memory Latency 84 7.4.1 Data Path Width 85 7.4.2 Caches 85 7.4.3 Interleaving 86 7.4.4 FastDRAMs 87 8 Interconnection Networks 89 8.1 System I/O 89 8.2 Inter-processor Communication 89 8.2.1 Bus 90 8.2.2 Mesh 91 8.2.3 Crossbar 92 8.2.4 Conclusion 93 iv 9 Examination of Architectures 94 9.1 Network of Workstations 94 9.1.1 NOW Model 94 9.1.2 Results 96 9.1.3 NOW Conclusions 97 9.2 General Purpose DSP Architecture 98 9.2.1 Processor 98 9.2.2 Memory 99 9.2.3 Interconnect 99 9.2.4 Sample Architecture 99 9.2.5 General Purpose DSP Conclusions 101 9.3 Vector DSP Architecture 101 9.3.1 Introduction to the LH9124 102 9.3.2 Single LH9124 Architectures 104 9.3.3 Range-Doppler Algorithm on a Single LH9124 Architecture 106 9.3.4 Multi-LH9124 Processor Architectures 107 9.3.5 Range Doppler Algorithm on Multi-LH9124 Architectures 108 9.3.6 Other Algorithms Ill 9.3.7 Vector DSP Conclusions 112 9.4 Optimized DSP Architecture 113 9.5 Digital Filter Chip Architecture 115 9.5.1 Architecture 115 9.5.2 Range and Azimuth Processing 117 9.5.3 Performance 118 9.5.4 Analysis 119 9.5.5 Digital Filter Conclusions 120 9.6 Fine Grained Parallel Architecture 121 9.7 A Heterogeneous Architecture 122 9.7.1 Vector Processor 124 9.7.2 Scalar Processor 125 9.7.3 Image Double Buffer 125 9.7.4 Data Movement 126 9.7.5 Implementation 126 9.7.6 Overall System 127 9.7.7 Range-Doppler Algorithm 128 9.7.8 Vector/Scalar Conclusions 130 9.8 FPGA Computing Machine 130 9.8.1 Standard Arithmetic 130 9.8.2 Distributed Arithmetic 131 9.8.3 FPGA Conclusions 133 9.9 Architecture Examination Conclusions 134 10 Conclusions and Future Work 138 10.1 Conclusions 138 10.2 Future Work 141 References 144 A Model of Range-Doppler Algorithm 150 List of Tables Table 2.1: Parameters of selected airborne radars 14 Table 2.2: Parameters of selected SAR satellites 15 Table 2.3: Attributes of some typical SAR processors 16 Table 2.4: Operation types 26 Table 2.5: Computational analysis of time domain algorithm 29 Table 2.6: Computational analysis of SPECAN algorithm 30 Table 2.7: Computational analysis of range-Doppler algorithm 31 Table 2.8: Computational analysis of wave equation algorithm 32 Table 2.9: Computational analysis of chirp scaling algorithm 33 Table 2.10: Approximate computational requirements for real-time processing 35 Table 2.11: Computational analysis of typical post-processing operations 36 Table 2.12: Range-Doppler model parameters 38 Table 5.1: High performance microprocessors and their FFT performance 63 Table 5.2: High performance DSPs and their FFT performance ..64 Table 5.3: FFT processor ICs 66 Table 5.4: High speed filter ICs 67 Table 5.5: Effect of memory chip size on chip and module count 69 Table 5.6: Bandwidth of some DRAM types ; 70 Table 5.7: Personal computer and workstation buses 71 Table 5.8: High speed buses and related interfaces 72 Table 5.9: Other high speed interfaces 72 Table 9.1: LH9124 execution times 103 Table 9.2: Range-Doppler algorithm implementation with a single LH9124 106 Table 9.3: Time domain processor performance 118 Table 9.4: Times for vector processor operations 129 Table 9.5: Scaling the distributed arithmetic filter 132 Table 9.6: Architecture trade-off 135 vi List of Figures Figure 2.1: General SAR geometry 5 Figure 2.2: Trajectory of point response 6 Figure 2.3: Block processing of SAR data 12 Figure 2.4: Main processing steps in some common SAR algorithms 18 Figure 2.5: Sample post-processing