3.5 GSPS Direct Digital Synthesizer with 12-Bit DAC Data Sheet AD9914 FEATURES FUNCTIONAL BLOCK DIAGRAM 3.5 GSPS internal clock speed AD9914 HIGH SPEED PARALLEL Integrated 12-bit DAC MODULATION Frequency tuning resolution to 190 pHz PORT 16-bit phase tuning resolution 12-bit amplitude scaling Programmable modulus Automatic linear and nonlinear frequency sweeping LINEAR SWEEP 3.5GSPS DDS CORE 12-BIT DAC capability BLOCK 32-bit parallel datapath interface 8 frequency/phase offset profiles Phase noise: −128 dBc/Hz (1 kHz offset at 1396 MHz) Wideband SFDR < −50 dBc Serial or parallel input/output control REF CLK 1.8 V/3.3 V power supplies MULTIPLIER TIMING AND CONTROL Software and hardware controlled power-down 88-lead LFCSP package PLL REF CLK multiplier SERIAL OR PARALLEL Phase modulation capability DATA PORT Amplitude modulation capability 10836-001 APPLICATIONS Figure 1. Agile LO frequency synthesis Programmable clock generator FM chirp source for radar and scanning systems Test and measurement equipment Acousto-optic device drivers Polar modulator Fast frequency hopping Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com AD9914* Product Page Quick Links Last Content Update: 04/12/2016 Comparable Parts Reference Materials View a parametric search of comparable partsView a Press parametric search of comparable parts • Analog Devices Advances RF and Microwave Designs from Bits to Antenna and Back at IMS2012 Evaluation Kits • Analog Devices Unveils Industry's Fastest 12-bit, Direct • AD9914 Evaluation Board Digital Synthesizers for Frequency-Agile Wireless Applications Documentation Product Selection Guide Application Notes • RF Source Booklet • AN-953: Direct Digital Synthesis (DDS) with a Programmable Modulus Design Resources User Guides • AD9914 Material Declaration • AD9914 Evaluation Board User Guide • PCN-PDN Information • Quality And Reliability Tools and Simulations • Symbols and Footprints • AD9914 IBIS Model Discussions View all AD9914 EngineerZone Discussions Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. 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AD9914 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDS Core .................................................................................... 19 Applications ....................................................................................... 1 12-Bit DAC Output .................................................................... 20 Functional Block Diagram .............................................................. 1 DAC Calibration Output ........................................................... 20 Revision History ............................................................................... 2 Reconstruction Filter ................................................................. 20 General Description ......................................................................... 3 Clock Input (REF_CLK/REF_CLK) ........................................ 21 Specifications ..................................................................................... 4 PLL Lock Indication .................................................................. 22 DC Specifications ......................................................................... 4 Output Shift Keying (OSK) ....................................................... 22 AC Specifications .......................................................................... 5 Digital Ramp Generator (DRG) ............................................... 23 Absolute Maximum Ratings ............................................................ 8 Power-Down Control ................................................................ 27 Thermal Performance .................................................................. 8 Programming and Function Pins ................................................. 28 ESD Caution .................................................................................. 8 Serial Programming ....................................................................... 31 Pin Configuration and Function Descriptions ............................. 9 Control Interface—Serial Input/Output ................................. 31 Typical Performance Characteristics ........................................... 12 General Serial Input/Output Operation .................................. 31 Equivalent Circuits ......................................................................... 16 Instruction Byte .......................................................................... 31 Theory of Operation ...................................................................... 17 Serial Input/Output Port Pin Descriptions ............................. 31 Single Tone Mode ....................................................................... 17 Serial Input/Output Timing Diagrams .................................... 32 Profile Modulation Mode .......................................................... 17 MSB/LSB Transfers .................................................................... 32 Digital Ramp Modulation Mode .............................................. 17 Parallel Programming (8-/16-Bit) ................................................ 33 Parallel Data Port Modulation Mode ....................................... 17 Register Map and Bit Descriptions .............................................. 34 Programmable Modulus Mode ................................................. 17 Register Bit Descriptions ........................................................... 39 Mode Priority .............................................................................. 18 Outline Dimensions ....................................................................... 45 Functional Block Detail ................................................................. 19 Ordering Guide .......................................................................... 45 REVISION HISTORY 1/16—Rev. D to Rev. E 7/13—Rev. A to Rev. B Changes to DDS Core Section ...................................................... 19 Change to CMOS Logic Outputs Parameter, Table 1 ................... 4 Change to Figure 30 ....................................................................... 19 Changes to Table 2 ............................................................................. 7 Updated Outline Dimensions ....................................................... 45 Changes to DDS Core Section ...................................................... 19 Changes to Phase-Locked Loop (PLL) Multiplier Section ....... 21 1/14—Rev. C to Rev. D Changed PLL Charge Pump Section to PLL Charge Pump/ Changes to Digital Timing Specifications Parameter, Table 2 .... 5 Total Feedback Divider Section; Changes to Table 8, PLL Changes to Figure 23 ...................................................................... 15 Loop Filter Components Section, and Figure 34 ....................... 22 Change to DAC Calibration Output Section .............................. 20 Change to Table 14 ......................................................................... 34 Change to Address 0x02, Table 14 ................................................ 34 Changes to Bits [15:8], Table 17 ................................................... 42 Changes to Table 17 ........................................................................ 41 8/12—Rev. 0 to Rev. A 11/13—Rev. B to Rev. C Changes to Features Section ............................................................ 1 Changes to Table 2 ............................................................................ 5 Changed Differential Input Voltage Unit from mV p-p to V p-p .... 4 Change to Programming and Function Pins Section ................ 30 Changes to Table 14 ....................................................................... 34 Changes to Table 16 ....................................................................... 40 Changes to Table 28 ....................................................................... 44 Updated Outline Dimensions ....................................................... 45 7/12—Revision 0: Initial Version Rev. E | Page 2 of 48 Data Sheet AD9914 GENERAL DESCRIPTION The AD9914 is a direct digital synthesizer (DDS) featuring a AD9914 via a serial or parallel input/output port. The AD9914 12-bit DAC. The AD9914 uses advanced DDS technology, also supports a user defined linear sweep mode of operation for coupled with an internal high speed, high performance DAC generating