October 15, 2019 W65C134S Datasheet W65C134S 8-bit Microcontroller WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Information contained herein is provided gratuitously and without liability, to any user. Reasonable efforts have been made to verify the accuracy of the information but no guarantee whatsoever is given as to the accuracy or as to its applicability to particular uses. In every instance, it must be the responsibility of the user to determine the suitability of the products for each application. WDC products are not authorized for use as critical components in life support devices or systems. Nothing contained herein shall be construed as a recommendation to use any product in violation of existing patents or other rights of third parties. The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales Policies, copies of which are available upon request. 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All rights reserved, including the right of reproduction in whole or in part in any form. www.WDC65xx.com 1 October 15, 2019 W65C134S Datasheet TABLE OF CONTENTS DOCUMENT REVISION HISTORY .................................................................................................................................. 5 1 INTRODUCTION ............................................................................................................................................................. 6 1.1 KEY FEATURES OF THE W65C134S ......................................................................................................... 6 2 W65C134S FUNCTION DESCRIPTION ........................................................................................................................ 6 2.1 Monitor ROM ............................................................................................................................................................... 6 2.2 SRAM ($0040-FF and $0140-FF) ............................................................................................................................... 7 2.3 Bus Control Register (BCR) ($001B) ....................................................................................................................... 7 Figure 2.3-1 BE Timing Relative to RESB Input. ............................................................................................. 7 Table 2.3-1 BCR7 and BE Control ..................................................................................................................... 7 2.3.1 Bus Control Register (BCR) Description ................................................................................................ 8 2.4 Port Chip Select 3 (PCS3) Register ($0007) ............................................................................................................ 9 2.4.1 Chip Select Register on Port 3 (PCS3) Description .............................................................................. 9 2.5 The Timers ................................................................................................................................................................ 10 2.5.1 Timer Control Register One (TCR1) Description ................................................................................. 11 2.5.2 Timer Control Register Two (TCR2) Description................................................................................. 12 2.6 Interrupt Flag Registers (IFR1, IFR2) ($002C, $0008) ........................................................................................... 13 2.6.1 Read of IFR1 and IFR2. ........................................................................................................................... 13 2.6.2 Interrupt Priority ....................................................................................................................................... 13 2.6.1 Interrupt Flag Register One (IFR1) Description ................................................................................... 13 2.6.2 Interrupt Flag Register One (IFR2) Description ................................................................................... 14 2.7 Interrupt Enable Registers (IER1, IER2) ($002D, $0009) ...................................................................................... 15 2.7.1 Interrupt Enable Register One (IER1) Description .............................................................................. 15 2.7.2 Interrupt Flag Register One (IER2) Description ................................................................................... 16 2.8 Universal Asynchronous Receiver/Transmitters (UARTs) ................................................................................. 17 2.8.1 Transmitter Operation ............................................................................................................................. 17 2.8.2 UART Data Register Description ........................................................................................................... 17 2.8.3 Transmitter Mode with Parity ................................................................................................................. 18 2.8.4 Receiver Operation .................................................................................................................................. 18 www.WDC65xx.com 2 October 15, 2019 W65C134S Datasheet 2.8.5 Data Timing for 7-bit Data without Parity and two stop bits. ............................................................. 18 2.8.6 UART RXD and TXD Data Rate Generation. ......................................................................................... 19 2.8.7 Asynchronous Control and Status Registers (ACSR) Description ................................................... 20 2.9 The Serial Interface Bus (SIB) ................................................................................................................................. 21 2.9.1 The STATE Register ................................................................................................................................ 21 2.9.2 STATE Register (STATE) Description ................................................................................................... 21 2.9.3 SR0, SR1, SR2, and SR3 Shift Register ................................................................................................ 22 Figure 2.9.3-1 SR0, SR1, SR2, and SR3 Shift Register ................................................................................. 22 2.9.4 SIB Shift Register Description ............................................................................................................... 22 2.9.5 SIB Control and Status Register (SCSR) .............................................................................................. 22 2.9.6 Sequence of events for the SIB message transmission. ................................................................... 24 Figure 2.9.6-1 Serial Interface Bus (SIB) Message Transmission Timing Diagram ................................. 26 Figure 2.9.6-2 Serial Interface Bus (SIB) Wiring Diagram ............................................................................ 27 Figure 2.9.6-3 Bus Address Register (BAR) .................................................................................................. 28 3 Memory Map ................................................................................................................................................................ 29 Table 3-1 System Memory Map ....................................................................................................................... 29 Table 3-2 I/O Memory Map ............................................................................................................................... 30 Table 3-3 Vector Table ..................................................................................................................................... 31 4 Pin List .......................................................................................................................................................................... 32 Table 4-1 68 Lead Pin Map (continued on next page) .................................................................................. 32 5 PIN FUNCTION DESCRIPTION................................................................................................................................... 34 Figure 5-1 Interface Diagram ........................................................................................................................... 34 Figure 5-2 68 Lead PLCC Pinout ..................................................................................................................... 35 Figure 5-3 80 Lead QFP Pinout ....................................................................................................................... 36 5.1 WEB Write Enable (WEB) (active low) ..................................................................................................... 37 5.2 RUN and SYNC outputs with WAI and STP defined (RUN) ................................................................... 37 5.3 FCLK ............................................................................................................................................................. 37 5.4 Phase 2 Clock Output (PHI2) ....................................................................................................................