CS 296-33: Intro to Programmable Logic and FPGAs ADEL EJJEH UNIVERSITY OF ILLINOIS URBANA-CHAMPAIGN © Adel Ejjeh, UIUC, 2015 2 Digital Logic • In CS 233: • Logic Gates • Build Logic Circuits • Sum of Products ?? F = (A’.B)+(B.C)+(A.C’) A B Black F Box C © Adel Ejjeh, UIUC, 2015 3 Programmable Logic Devices (PLDs) PLD PLA PAL CPLD FPGA (Programmable (Programmable (Complex PLD) (Field Prog. Logic Array) Array Logic) Gate Array) •2-level structure of •Enhanced PLAs •For large designs •Has a much larger # of AND-OR gates with reduced costs •Collection of logic blocks with programmable multiple PLDs with •Larger interconnection connections an interconnection networK structure •Largest manufacturers: Xilinx - Altera Slide taken from Prof. Chehab, American University of Beirut © Adel Ejjeh, UIUC, 2015 4 Combinational Programmable Logic Devices PLAs, CPLDs © Adel Ejjeh, UIUC, 2015 5 Programmable Logic Arrays (PLAs) • 2-level AND-OR device • Programmable connections • Used to generate SOP • Ex: 4x3 PLA Slide adapted from Prof. Chehab, American University of Beirut © Adel Ejjeh, UIUC, 2015 6 PLAs contd • O1 = I1.I2’ + I4.I3’ • O2 = I2.I3.I4’ + I4.I3’ • O3 = I1.I2’ + I2.I1’ Slide adapted from Prof. Chehab, American University of Beirut © Adel Ejjeh, UIUC, 2015 7 Programmable Array Logic (PALs) • More Versatile than PLAs • User Programmable AND array followed by fixed OR gates • Flip-flops/Buffers with feedback transforming output ports into I/O ports © Adel Ejjeh, UIUC, 2015 8 Complex PLDs (CPLD) • Programmable PLD blocks (PALs) I/O Block I/O I/O Block I/O PLD PLD • • • Programmable Interconnects • Block Block • • • Interconnection Matrix I/O Block I/O I/O Block I/O PLD PLD • • • Block Block • • • © Adel Ejjeh, UIUC, 2015 9 What About Sequential Circuits? Application Specific Field Programmable Integrated Circuits Gate Arrays General Purpose Computers (ASICS) (FPGAs) Pros: Bridges the gap between Pros: • • • Very High Performance ASICS and General • HighlyHighly programmable/flexibleprogrammable/flexible • (Fast, Efficient, …) Purpose Computes • CheapCheap (relatively) (relatively) Cons: Combines flexibility of Cons: • No Programmability/flexibility Computers with •• NotNotasas fast fast as as ASICS ASICS • Very Expensive Performance of ASICs (Software(Software not not asas fast fast as as hardware!) hardware!) © Adel Ejjeh, UIUC, 2015 10 Sequential Programmable Logic Devices FPGAs © Adel Ejjeh, UIUC, 2015 11 Field Programmable Gate Arrays • Sequential Programmable Logic Circuits • Configurable Logic Blocks (CLBs) • Programmable Interconnect • Specialized Resources 16-bit SR • Multipliers/DSP Blocks 16x1 RAM a 4-input LUT b • y Fast Memories (Block RAM) c mux d flip-flop • Clock Buffers q e • I/O clock clock enable set/reset © Adel Ejjeh, UIUC, 2015 12 What are Look Up Tables (LUTs)? • LUT is a RAM! Truth Table a b c y Programmed LUT Required Function 0 0 0 1 LUT 0 0 1 0 1 a 0 1 0 1 0 b y 1 0 1 1 1 1 c MUX y 1 0 0 1 1 0 yabc=•+ 1 0 1 0 1 1 1 1 0 1 a,b,c 1 1 1 1 Slide adapted from Serge karabchevsky: Programmable Logic and FPGA © Adel Ejjeh, UIUC, 2015 13 Xilinx FPGAs • Historically, two families: • Virtex: High performance, very expensive • Spartan: Lower end, not as expensive as Virtex • Today, offer three families: • Virtex • Kintex: Mid-range FPGA, new family • Artix: Replaced Spartan as the lower end FPGA Family • Series: 7 • Most upcoming slides taken from Xilinx Workshops © Adel Ejjeh, UIUC, 2015 14 Xilinx 7-series Architecture Overview Artix-7 Architecture Overview © Adel Ejjeh, UIUC, 2015 15 Configurable Logic Blocks (CLB) • Primary resource for design in Xilinx FPGAs • Combinatorial functions • Flip-flops • CLB contains two slices • Each slice can be (SLICEM, SLICEL) • Connected to switch matrix for routing to other FPGA resources • Carry chain runs vertically in a column from one slice to the one above © Adel Ejjeh, UIUC, 2015 16 Slice Resources • Four six-input Look-Up Tables (LUT) • Multiplexers • Used to implement 7 and 8 input functions • Carry chains • Used to implement fast arithmetic addition/subtraction • Flip-flops/latches • 4 FF/L, 4 FF © Adel Ejjeh, UIUC, 2015 17 Look Up Tables (LUTs) • Used as conventional LUTs in SLICEL • Implement 1 6-input function or 2 5-input functions • How it works: • Basically a bunch of SRAM cells • Saves the outputs of truth table in each cell • Combination of inputs select the correct cell and thus output is read • Can be used as either Memory or Shift Register in SLICEM • Not used in our case © Adel Ejjeh, UIUC, 2015 18 Other Resources • Block RAM used for close/fast storage or as FIFO • DSP48E1 Slice: High Performance Arithmetic Block © Adel Ejjeh, UIUC, 2015 19 So What? • How do we program them? • Each manufacturer has their own set of tools • Write HDL (Verilog/VHDL) and synthesize onto FPGA • Provides extra efficiency by manual Place and Route • Tool-chain will generate ”bit stream” which is used to program FPGA • After programming, FPGA will be like a “Hardware Entity” performing specific functions defined in HDL. • Recently, tools providing support for High Level Synthesis • Write High Level Language (C/C++, OpenCL, myHDL) © Adel Ejjeh, UIUC, 2015 20 What we will do? • Use Vivado HLS (Xilinx tool-chain) to synthesize Verilog • Program synthesized Verilog onto Basys 3 Xilinx FPGA • Experiment with different labs ranging from simple combinational circuits to FSMs © Adel Ejjeh, UIUC, 2015 21 Rough Timeline • March 4: Intro to FPGAs (Today) • March 11: MIPS++ (Purajit) • March 18: Intro to Vivado and Tutorial • Apr 8: Lab 1 • Apr 15: Lab 2 • Apr 22: Lab 3 • I will send out a whenisgood email to set a time for labs: • 2 hour meetings • No Lecture same week.