Implementation And Evaluation Of An RF Receiver Architecture Using An Undersampling Track-And-Hold Circuit Magnus Dahlbäck LiTH-ISY-EX-3448-2003 Linköping 5 January 2004 Implementation And Evaluation Of An RF Receiver Architecture Using An Undersampling Track-And-Hold Circuit Examensarbete utfört i Elektroniksystem vid Linköpings tekniska högskola av Magnus Dahlbäck LiTH-ISY-EX-3448-2003 Handledare: Mark Vesterbacka Examinator Mark Vesterbacka Linköping 2004-01-05 Datum Avdelning, Institution Date Division, Department 2003-12-18 Institutionen för systemteknik 581 83 LINKÖPING Språk Rapporttyp ISBN Language Report category Svenska/Swedish Licentiatavhandling ISRN LITH-ISY-EX-3448-2003 X Engelska/English X Examensarbete C-uppsats Serietitel och serienummer ISSN D-uppsats Title of series, numbering Övrig rapport ____ URL för elektronisk version http://www.ep.liu.se/exjobb/isy/2003/3448/ Titel Implementation och utvärdering av en RF-mottagare baserad på en undersamplande Title track-and-hold-krets Implementation and Evaluation of an RF Receiver Architecture Using an Undersam- pling Track-and-Hold Circuit Författare Magnus Dahlbäck Author Sammanfattning Abstract Today's radio frequency receivers for digital wireless communication are getting more and more complex. A single receiver unit should support multiple bands, have a wide bandwidth, be flexible and show good performance. To fulfil these requirements, new receiver architectures have to be developed and used. One possible alternative is the RF undersampling architecture. This thesis evaluates the RF undersampling architecture, which make use of an undersampling track-and-hold circuit with very wide bandwidth to perform direct sampling of the RF carrier before the analogue-to-digital converter. The architecture’s main advantages and drawbacks are identified and analyzed. Also, techniques and improvements to solve or reduce the main problems of the RF undersampling receiver are proposed. Nyckelord Keyword RF, track-and-hold, undersampling, receiver, noise folding, harmonics aliasing Magnus Dahlbäck 5/1/04 Abstract Todays’ radio frequency receivers for digital wireless communication are getting more and more complex. A single receiver unit should support multiple bands, have a wide bandwidth, be flexible and show good performance. To fulfil these requirements, new receiver architectures have to be developed and used. One possible alterna- tive is the RF undersampling architecture. The RF undersampling architecture, which make use of an under- sampling track-and-hold circuit with very wide bandwidth to per- form direct sampling of the RF carrier before the analogue-to-digital converter, is evaluated in this thesis. The architecture’s main advan- tages and drawbacks are identified and analyzed. Also, techniques and improvements to solve or reduce the main problems of the RF undersampling receiver are proposed. Magnus Dahlbäck 5/1/04 Magnus Dahlbäck 5/1/04 1 Introduction . 1 1.1 Background . 1 1.2 Assignment. 2 1.2.1 Main Thesis Questions. 2 1.2.2 Motivation For The GSM900 Choice . 2 1.3Method . 3 1.3.1 Prestudy . 3 1.3.2 Measurements . 3 1.3.3 Evaluation . 3 1.4 Limitations . 3 1.5 Disposition . 4 1.6 Reading instructions. 4 2 RF Receiver Basics . 5 2.1 RF Overview. 5 2.2 The Generic RF Receiver. 5 2.3Theory Concepts . 6 2.3.1 Noise Figure. 6 2.3.2 Sensitivity. 7 2.3.3 Harmonic Distortion . 8 2.3.4 Intermodulation . 9 2.3.5 Third-Order Intercept Point. 11 3 Mixer-Based Receiver Architectures. 13 3.1 The Mixer - An Introduction . 13 3.1.1 Downconversion. 13 3.1.2 Image Response . 14 3.1.3 LO Leakage . 14 3.1.4 Half-IF Response . 15 3.1.5 LO Spurious Responses . 15 3.2 The Superheterodyne Architecture. 16 3.2.1 Component Density . 16 3.2.2 Sensitivity And Selectivity. 16 3.3 The Direct-Conversion Architecture . 17 3.3.1 Noise and Distortion Performance . 17 3.3.2 Component Density . 18 Table of Contents Magnus Dahlbäck 5/1/04 4 The RF Undersampling Architecture. 19 4.1 Architecture Overview . 19 4.1.1 Undersampling . 20 4.1.2 Downconversion By Undersampling . 22 4.2 Advantages . 23 4.2.1 Less Analogue Processing. 23 4.2.2 Multiple Frequency Bands . 24 4.2.3Flexibility . 25 4.3Noise Folding . 25 4.3.1 SNR Degradation . 26 4.3.2 Sample Frequency Considerations . 27 4.3.3 Front-End Gain. 28 4.3.4 Further Reduction Of Performance Loss . 29 4.3.5 Clock Noise . 31 4.4 Harmonics Aliasing. 32 4.4.1 Low-Pass Filtering . 34 4.4.2 Changing Sample Frequencies . 34 4.5 T/H and ADC Integration Considerations . 35 4.5.1 Sample Clocks Frequencies. 35 4.5.2 Clocks Phase Difference . 35 5 Measurement Results . 37 5.1 Measurements Setup . 37 5.1.1 The T/H Circuit . 37 5.1.2 T/H Measurements Setup . 39 5.1.3T/H And ADC Integration Measurement Setup . 40 5.2 T/H Measurement Results . 42 5.2.1 Downconversion. 42 5.2.2 Noise Folding . 43 5.2.3Noise Figure. 46 5.2.4 Harmonic Distortion . 46 5.2.5 Two-Tone Intermodulation Distortion . 48 5.3T/H And ADC Integration Measurement Results . 49 5.3.1 Clocks Phase Difference . 49 5.3.2 Spectrum Response. 50 5.3.3 Spectrum Response With Intermediate Filtering 51 Table of Contents Magnus Dahlbäck 5/1/04 6 Conclusions. 55 6.1 Future Work . 56 6.1.1 Differential Signalling . 56 6.1.2 Double Scanning . 56 6.1.3Variable Sample Frequencies . 58 7 References . 59 7.1 Recommended Literature. 59 Table of Contents Magnus Dahlbäck 5/1/04 Table of Contents Magnus Dahlbäck 5/1/04 List of Figures Figure 2-1. The front-end, the analogue-to-digital interface and the Digital processing hardware.................... 6 Figure 2-2. Harmonic distortion. ............................................. 8 Figure 2-3. Power changes for harmonic signals. .................. 9 Figure 2-4. Second- and third-order intermodulation products................................................................ 10 Figure 2-5. Third-order IMD rejection ratio. ............................ 10 Figure 2-6. Floor of in-band IMD products.............................. 11 Figure 2-7. Distortion from adjacent channels........................ 11 Figure 2-8. Third-order intercept point.................................... 12 Figure 3-9. Frequency translation in a mixer. ......................... 13 Figure 3-10. The image signal.................................................. 14 Figure 3-11. LO leakage to RF input. ....................................... 14 Figure 3-12. Half-IF spurious response. ................................... 15 Figure 3-13. LO spurious responses. ....................................... 15 Figure 3-1. The typical superheterodyne architecture. ........... 16 Figure 3-2. The typical direct-conversion architecture............ 17 Figure 4-1. The RF undersampling architecture..................... 19 Figure 4-2. The wide-band track-and-hold in front of the ADC...................................................................... 20 Figure 4-3. Frequency response of Nyquist sampling. ........... 21 Figure 4-4. Aliasing distortion. ................................................ 21 Figure 4-5. Frequency spectrum before undersampling......... 22 Figure 4-6. Downconversion by undersampling. .................... 22 Figure 4-7. Functional diagram for support of multiple RF bands.................................................................... 24 Figure 4-8. Signal spectrum before noise folding. .................. 25 Figure 4-9. Signal spectrum after noise folding. ..................... 25 Figure 4-10. Modelled SNR degradation versus sample frequency.............................................................. 27 Figure 4-11. total noise figure versus T/H noise figure and front-end gain. ...................................................... 29 Figure 4-12. Modelled SNR degradation due to noise folding versus difference between in-band and out-band noise power density.............................................. 30 Figure 4-13. Expected T/H output spectrum for GSM downlink. .............................................................. 32 Figure 4-14. Expected ADC output spectrum for GSM downlink. .............................................................. 33 Magnus Dahlbäck 5/1/04 Figure 4-15. Aliasing of second-order harmonics..................... 33 Figure 4-16. Elimination of harmonics aliasing by low-pass filtering.................................................................. 34 Figure 4-17. Changing clock frequency may solve harmonics aliasing. ................................................................ 34 Figure 4-18. T/H output and ADC sampling.............................. 35 Figure 5-1. RTH010 functional diagram.................................. 37 Figure 5-2. Close-up of the T/H PCB...................................... 39 Figure 5-3. T/H measurements setup..................................... 39 Figure 5-4. TH1 and TH2 out-of-phase clocking..................... 40 Figure 5-5. The MP4 PCI card mounted in a PC.................... 41 Figure 5-6. T/H and ADC clocking.......................................... 41 Figure 5-7. T/H output spectrum confirms downconversion by undersampling...................................................... 42 Figure 5-8. T/H output spectrum for GSM Downlink signal in first nyquist zone when sample frequency is 204.8 MHz............................................................ 43 Figure 5-9. T/H output spectrum for GSM Downlink signal in first nyquist zone when sample frequency is 819.2 MHz............................................................ 44 Figure 5-10. Measured SNR degradation versus. sample frequency. ...........................................................