Intel® Itanium® 2 Processor Hardware Developer’s Manual July 2002 Document Number: 251109-001 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Itanium 2 processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://developer.intel.com/design/litcentr. Intel and Itanium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Copyright © 2002, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. I2C is a two-wire communication bus /protocol developed by Phillips. SMBus is a subset of the I2C bus/protocol developed by Intel. Implementation of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Phillips Electronics, N.V. and North American Phillips Corporation. ii Intel® Itanium® 2 Processor Hardware Developer’s Manual Contents 1 Introduction......................................................................................................................1-1 1.1 Itanium® 2 Processor System Bus .....................................................................1-1 1.2 Processor Abstraction Layer ..............................................................................1-1 1.3 Terminology........................................................................................................1-2 1.4 Reference Documents........................................................................................1-2 1.4.1 Revision History ....................................................................................1-3 2 Itanium® 2 Processor Microarchitecture..........................................................................2-1 2.1 Overview ............................................................................................................2-1 2.1.1 6-Wide EPIC Core.................................................................................2-1 2.1.2 Processor Pipeline ................................................................................2-2 2.1.3 Processor Block Diagram......................................................................2-3 2.2 Instruction Processing ........................................................................................2-4 2.2.1 Instruction Prefetch and Fetch ..............................................................2-4 2.2.2 Branch Prediction ..................................................................................2-5 2.2.3 Dispersal Logic......................................................................................2-5 2.3 Execution............................................................................................................2-5 2.3.1 Floating-Point Unit (FPU) ......................................................................2-5 2.3.2 Integer Logic..........................................................................................2-6 2.3.3 Register Files ........................................................................................2-6 2.3.4 Register Stack Engine (RSE) ................................................................2-7 2.4 Control................................................................................................................2-8 2.5 Memory Subsystem............................................................................................2-8 2.5.1 L1 Instruction Cache .............................................................................2-9 2.5.2 L1 Data Cache ......................................................................................2-9 2.5.3 Unified L2 Cache...................................................................................2-9 2.5.4 Unified L3 Cache...................................................................................2-9 2.5.5 The Advanced Load Address Table (ALAT)..........................................2-9 2.5.6 Translation Lookaside Buffers (TLBs) .................................................2-10 2.5.7 Cache Coherency................................................................................2-10 2.5.8 Write Coalescing .................................................................................2-10 2.5.9 Memory Ordering ................................................................................2-11 2.6 IA-32 Execution................................................................................................2-11 3 System Bus Overview .....................................................................................................3-1 3.1 Signaling on the Itanium® 2 Processor System Bus ..........................................3-1 3.1.1 Common Clock Signaling ......................................................................3-1 3.1.2 Source Synchronous Signaling .............................................................3-2 3.2 Signal Overview .................................................................................................3-3 3.2.1 Control Signals ......................................................................................3-4 3.2.2 Arbitration Signals .................................................................................3-4 3.2.3 Request Signals ....................................................................................3-5 3.2.4 Snoop Signals .......................................................................................3-5 3.2.5 Response Signals .................................................................................3-6 3.2.6 Data Signals ..........................................................................................3-7 3.2.7 Defer Signals.........................................................................................3-8 3.2.8 Error Signals..........................................................................................3-8 3.2.9 Execution Control Signals .....................................................................3-9 Intel® Itanium® 2 Processor Hardware Developer’s Manual iii 3.2.10 IA-32 Compatibility Signals ...................................................................3-9 3.2.11 Platform Signals ..................................................................................3-10 3.2.12 Diagnostic Signals...............................................................................3-10 4 Data Integrity...................................................................................................................4-1 4.1 Error Classification .............................................................................................4-1 4.2 Itanium® 2 Processor System Bus Error Detection............................................4-1 4.2.1 Bus Signals Protected Directly..............................................................4-2 4.2.2 Bus Signals Protected Indirectly ...........................................................4-2 4.2.3 Unprotected Bus Signals.......................................................................4-3 4.2.4 Itanium® 2 Processor System Bus Error Code Algorithms ...................4-3 5 Configuration and Initialization ........................................................................................5-1 5.1 Configuration Overview......................................................................................5-1 5.2 Configuration Features.......................................................................................5-1 5.2.1 Data Bus Error Checking ......................................................................5-2 5.2.2 Response/ID Signal Parity Error Checking ...........................................5-2 5.2.3 Address/Request Signal Parity Error Checking.....................................5-3 5.2.4 BERR# Assertion for Initiator Bus Errors ..............................................5-3 5.2.5 BERR# Assertion for Target Bus Errors................................................5-3 5.2.6 BERR# Sampling ..................................................................................5-3 5.2.7 BINIT# Error