International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 1 Issue 9, November- 2012 Performance Evaluation Of Strained Si/Sige N-Channel Mosfet 1 Rakhi Sharma, 2 Ajay Kumar Yadav, 3 Dr.D.B.Ojha, 4Vishal Upmanu Mewar University, Chittorgarh (Raj.) functional form and lends itself to efficient computation. Concept of strained silicon and ABSTRACT effects due to germanium concentration in device parameters are also studied in this work Strained Si/SiGe n-channel MOSFET has tremendous Electronics, and in particular the applications in biomedical field. The modern integrated circuit has made possible the design of communication world is also taking interest to use powerful and flexible processors which provide strained Si/SiGe n-channel MOSFET in its highly intelligent and adaptable devices for the applications because of high speed of operation user. Integrated circuit memories fabricated by using MOS (Metal-Oxide-Semiconductor) INTRODUCTION technology have provided the essential elements to complement these processors and, together Electronics is characterized by with a wide range of logic and analog integrated reliability, low power dissipation, circuitry. N MOS technology has an important role extremely low weight and volume, and in IC fabrication. Works are going on to improve low cost, coupled with an ability to the performance of n MOSFETs. Device scaling cope easily with a high degree of which was a major driving force in the sophistication and complexity. development of high density ICs is facing a numberIJERT Electronics, and in particular the of obstacles, making it very difficult to sustain the IJERT integrated circuit has made possible the trend of device performance improvements. design of powerful and flexible Consequently, innovative device structures and processors which provide highly materials are actively being investigated to boost intelligent and adaptable devices for performance. The tensile-strained-Si MOSFET is the user. Integrated circuit memories getting attention recently, as it significantly fabricated by using MOS (Metal-Oxide- enhances the inversion layer electron mobility Semiconductor) technology have and hence the performance of deep provided the essential elements to submicron MOSFETs for high speed complement these processors and, operations. One of the suggestions from together with a wide range of logic and researcher was to develop a strained SiGe analog integrated circuitry. Within the channel structure grown on a normal Si bounds of MOS technology the possible circuit realizations may be based on p- substrate. These SiGe-channel MOSFET’s MOS, n-MOS and BiCMOS devices. show some significantly better electrical Although CMOS is the dominant characteristics as compared to the silicon- technology, but emphasis is given to channel MOSFET’s. In this performance of a nMOS technology. The reasons for this strained Si/SiGe n-Channel MOSFET has been are as follows slightly less than the studied on the basis of ORCAD simulations. dielectric constant εr of the substrate Parameters needed for the simulations were first because the fringing fields from the obtained on the basis of analytical model. Physics patch to the ground plane are not based 2-D model for the surface potential confined in the dielectric only, but are variation along the channel in an n-channel SiGe also spread in the air. MOSFET’s is developed by solving the two- dimensional Poisson’s equation. It is simple in its www.ijert.org 1 International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 1 Issue 9, November- 2012 If the design of nMOS technology is to be currents. Figure shows the impact of Ge in the carried out effectively or the performance of lattice of silicon when SiGe layer is formed. circuits based on it is to be understood than one must have a sound knowledge of MOS active device. For the performance improvement of n- MOS device, since last 3 decades scaling has been the primary means. However, device scaling is facing a number of obstacles, making it very difficult to sustain the trend of device performance improvements. Consequently, innovative device structures and materials are actively being investigated to boost performance [1], [2]. The tensile-strained-Si MOSFET is getting attention recently, as it significantly enhances the inversion layer electron mobility and hence the performance of deep submicron MOSFETs for high speed operations. One of the suggestions from researcher was to develop a strained SiGe channel structure grown on a normal Si substrate [3], [4]. A SiGe layer of several nm thick provides the big advantage that only a small change from the Figure : (a) Ge is introduced into the lattice (b) Si standard fabrication process is needed for electron is deposited on top of the SiGe. Atoms align mobility enhancement. High-speed devices require a large charging current that is now obtained by causing a strain in the lattice. increasing their carrier mobility with the introduction of SiGe layer. CONCEPT OF STRAINED SILICON ANALYSIS AND DESIGN MATHEMATICAL FORMULATION FOR The tensile-strained-Si MOSFET is gettingIJERT IJERT attention recently, as it significantly enhances the SURFACE POTENTIAL inversion layer electron mobility and hence the performance of deep submicron MOSFETs. The strained-Si MOSFETs exhibit a shifted threshold As (x, y)i (x, y)i (x) is voltage from conventional Si devices, due to the band offset at the heterojunction between the defined as the intrinsic potential at a point x, y strained-Si and SiGe layers. The strain of Si is with respect to the intrinsic potential of the p-type obtained from a Si layer grown epitaxially on a substrate [46].The substrate is assumed to be relaxed Si Ge layer. A chemical mechanical uniformly doped with a concentration Na . polishing (CMP) step is introduced in the middle of SiGe epitaxy to reduce the surface roughness. In the oxide region AFGH, Poisson’s Overall thermal budget and etch steps can be equation becomes a homogeneous (Laplace) equation, controlled tightly to minimize strain relaxation, Ge out-diffusion, and strained-Si consumption [37]. Relaxed Si1-xGex graded buffers can be used as a template for epitaxially growing Si in a state of 2 2 biaxial tensile strain and n-type MOSFETs (1) 2 + 2 = 0 fabricated on strained-silicon Si x y demonstrate higher effective mobility than those on Czochralski-grown Si (Cz-Si) [49]. Even in devices with high channel doping and short gate In the depletion region in silicon, the lengths, the strain-induced electron mobility concentrations of both types of mobile carriers are enhancement leads directly to increased drive negligible under subthreshold conditions. www.ijert.org 2 International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 1 Issue 9, November- 2012 Therefore, in ABEF, Poissin’s equation is Where Vg and Vds are the gate and approximated by- source-drain voltages. V fb is the flat-band voltage of the gate electrode, and bi is the built- 2 2 qN in potential of the source- or drain-to-substrate + = a (2) 2 2 junction. For an abrupt n+-p x y SiGe junction, bi Eg / 2q B , KT N The length of the SiGe region is equal to the where a . B ln channel length L. the depth is given by the q Ni depletion layer width,Wd , to be determined later.As the normal component of the electric field The bottom boundary is movable one, as will changes by a factor of / 3 across SiGe ox change with the gate voltage . The distance BC the silicon-oxide boundary AF [46]. To eliminate is approximately given by the source junction this boundary condition so that and its depletion width, derivatives are continuous, the oxide is replaced by an equivalent region of the same dielectric constant as SiGe, but with the thickness equal 2 to3 tox. This preserves the capacitance and allows siGe bi Ws = (6) the entire rectangular region to be treated as a qN a homogeneous material of dielectric constant SiGe . The drawback is that it may cause Similarly, DE is given by the drain junction some error in tangential field, whose magnitude depletion width, does not change across the silicon-oxide boundary. In the equivalent structure, the tangential field 2 si ( bi Vds ) W Ge (7) apparently experiences a thicker-than-actualIJERT D qN oxide. The errors are expected to be smaller when IJERT a the gate oxide is thin compared to the silicon depletion depth W so that the oxide field is d The boundary conditions along FG and HA dominated by its normal component. are assumed to very linearly between the end point values, while those along BC and BE are If the source and drain junctions are abrupt and assumed to vary parabolically between the end deeper thanWd , the set of simplified boundary points.The surface potential solution technique conditions will be as follows: makes use of the superposition principle and breaks the electrostatic potential into the (3tox , y)Vg V fb following terms.Here v(x, y) is a solution to the along GH. inhomogeneous (4.3) (Poisson’s) equation and satisfies the top boundary condition, Equation . u ,u ,u are solutions to homogeneous (x,0)bi L R B along AB. (3) (Laplace) equation, and are chosen in order for (x, y) to satisfy the rest of the boundary (x,L)bi condition namely, on the left, the right, and the along EF. (4) A natural choice for is approximated as: (Wd , y)0 along CD. (5) www.ijert.org 3 International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 1 Issue 9, November- 2012 This point corresponds to the point of Vg V fb S v(x, y) S maximum barrier height. It is close to the mid 3tox point of the channel when the drain voltage is low.