Second Generation Intel® Xeon® Scalable Processors Datasheet, Volume One: Electrical April 2019 Reference Number: 338845-001US IntelLegal Lines and Disclaimerstechnologies features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Learn more at intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. 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All Rights Reserved. 2 Second Generation Intel® Xeon® Scalable Processors Datasheet, Volume One: Electrical, April 2019 Contents 1Introduction..............................................................................................................7 1.1 Electrical Specification Introduction........................................................................7 1.2 Related Publications.............................................................................................8 1.3 Terminology .......................................................................................................8 1.4 Statement of Volatility (SOV) .............................................................................. 11 2 Electrical Specifications ........................................................................................... 13 2.1 Integrated Voltage Regulation............................................................................. 13 2.2 Processor Signaling ........................................................................................... 13 2.2.1 System Memory Interface Signal Groups ................................................... 13 2.2.2 PCI Express* Signals .............................................................................. 13 2.2.3 DMI3/PCI Express Signals ....................................................................... 14 2.2.4 Intel® Ultra Path Interconnect (Intel® UPI)............................................... 14 2.2.5 Platform Environmental Control Interface (PECI) ........................................ 14 2.2.6 System Reference Clocks (BCLK{0/1/2}_DP, BCLK{0/1/2}_DN)15 2.2.7 JTAG and Test Access Port (TAP) Signals ................................................... 15 2.2.8 Processor Sideband Signals ..................................................................... 15 2.2.9 Power, Ground and Sense Signals............................................................. 16 2.2.10 Reserved or Unused Signals..................................................................... 27 2.3 Signal Group Summary ...................................................................................... 28 2.4 Fault Resilient Booting (FRB)............................................................................... 31 2.4.1 Power-On Configuration (POC) Options...................................................... 32 2.5 Mixing Processors.............................................................................................. 33 2.6 Flexible Motherboard Guidelines (FMB) ................................................................. 33 2.7 Absolute Maximum and Minimum Ratings ............................................................. 33 2.7.1 Storage Conditions Specifications ............................................................. 34 2.8 DC Specifications .............................................................................................. 35 2.8.1 Voltage and Current Specifications............................................................ 35 2.8.2 Die Voltage Validation ............................................................................. 40 2.8.3 Signal DC Specifications .......................................................................... 41 2.9 Package C-State Power Specifications .................................................................. 47 2.10 Signal Quality ................................................................................................... 48 2.10.1 DDR Signal Quality Specifications ............................................................. 48 2.10.2 PCIe Signal Quality Specifications ............................................................. 48 2.10.3 Intel® Ultra Path Interconnect (Intel® UPI) Signal Quality Specifications....... 48 2.10.4 Input Reference Clock Signal Quality Specifications..................................... 49 2.10.5 Overshoot/Undershoot Tolerance.............................................................. 49 3 Processor Land Listing............................................................................................. 53 4 Signal Descriptions.................................................................................................. 55 4.1 System Memory Interface .................................................................................. 55 4.2 PCI Express* Based Interface Signals................................................................... 56 4.3 DMI3 Signals .................................................................................................... 56 4.4 Intel® Ultra Path Interconnect (Intel® UPI) Signals............................................... 57 4.5 PECI Signal ...................................................................................................... 57 4.6 System Reference Clock Signals .......................................................................... 57 4.7 JTAG and TAP Signals ........................................................................................ 57 4.8 Serial VID Interface (SVID) Signals...................................................................... 58 4.9 Processor Asynchronous Sideband and Miscellaneous Signals .................................. 58 4.10 Processor Power and Ground Supplies .................................................................. 62 5PIROM..................................................................................................................... 65 Second Generation Intel® Xeon® Scalable Processors 3 Datasheet, Volume One: Electrical, April 2019 5.1 Processor Information ROM .................................................................................65 5.2 Scratch EEPROM ................................................................................................67 5.3 PIROM and Scratch EEPROM Supported SMBus Transactions....................................67 5.4 SMBus Memory Component Addressing.................................................................68 5.4.1 Managing Data in the PIROM ....................................................................68 5.4.2 Header ..................................................................................................69 5.4.3 Processor Data .......................................................................................72 5.4.4 Processor Core Data................................................................................73 5.4.5 Processor Uncore Data ............................................................................75 5.4.6 Processor Cache Data..............................................................................77 5.4.7 Package Data .........................................................................................78 5.4.8 Processor Voltage Data............................................................................78 5.4.9 Part Number Data...................................................................................82 5.4.10 Thermal Reference Data ..........................................................................84 5.4.11 Feature Data..........................................................................................85 5.4.12 Protected Processor Inventory Number ......................................................87 5.4.13 Checksums ............................................................................................88 A Pin Listing................................................................................................................89 Figures 2-1 Input Device Hysteresis ......................................................................................14 2-2 VCCIN Static and Transient Tolerance Load Lines 0.9 mOHM....................................39