Low Latency Ethernet 10G MAC User Guide Last updated for Altera Complete Design Suite: 14.1 Subscribe UG-01144 101 Innovation Drive 2014.12.15 San Jose, CA 95134 Send Feedback www.altera.com TOC-2 Low Latency Ethernet 10G MAC User Guide Contents About this IP Core...............................................................................................1-1 Features......................................................................................................................................................... 1-1 Release Information.....................................................................................................................................1-2 Device Family Support................................................................................................................................1-3 Performance and Resource Utilization.....................................................................................................1-4 Transmit and Receive Latencies.................................................................................................................1-5 Getting Started.................................................................................................... 2-1 Introduction to Altera IP Cores.................................................................................................................2-1 Installing and Licensing IP Cores..............................................................................................................2-2 Specifying IP Core Parameters and Options............................................................................................2-2 Parameterizing the IP Core........................................................................................................................ 2-3 Parameter Settings....................................................................................................................................... 2-4 Generated Files.............................................................................................................................................2-7 Simulating Altera IP Cores in other EDA Tools..................................................................................... 2-7 Upgrading Outdated IP Cores................................................................................................................... 2-9 Migrating IP Cores to a Different Device.................................................................................................2-9 LL Ethernet 10G MAC Design Considerations.....................................................................................2-10 Migrating from Ethernet 10G MAC to LL Ethernet 10G MAC..............................................2-10 Timing Constraints........................................................................................................................2-11 Functional Description....................................................................................... 3-1 Architecture.................................................................................................................................................. 3-1 Interfaces....................................................................................................................................................... 3-2 Frame Types..................................................................................................................................................3-4 Transmit Datapath.......................................................................................................................................3-4 Padding Bytes Insertion.................................................................................................................. 3-4 Address Insertion.............................................................................................................................3-4 CRC-32 Insertion.............................................................................................................................3-5 XGMII Encapsulation..................................................................................................................... 3-6 Inter-Packet Gap Generation and Insertion................................................................................ 3-7 XGMII Transmission...................................................................................................................... 3-7 Unidirectional Feature.................................................................................................................... 3-8 TX Timing Diagrams.......................................................................................................................3-9 Receive Datapath........................................................................................................................................3-13 Minimum Inter-Packet Gap ........................................................................................................3-13 XGMII Decapsulation................................................................................................................... 3-13 CRC Checking................................................................................................................................3-14 Address Checking.......................................................................................................................... 3-14 Frame Type Checking................................................................................................................... 3-14 Length Checking............................................................................................................................ 3-15 Altera Corporation Low Latency Ethernet 10G MAC User Guide TOC-3 CRC and Padding Bytes Removal................................................................................................3-16 Overflow Handling........................................................................................................................ 3-16 RX Timing Diagrams.................................................................................................................... 3-17 Flow Control...............................................................................................................................................3-18 IEEE 802.3 Flow Control.............................................................................................................. 3-18 Priority-Based Flow Control........................................................................................................ 3-20 PHY Configurations..................................................................................................................................3-21 10GBASE-R Register Mode..........................................................................................................3-22 Error Handling (Link Fault).....................................................................................................................3-23 IEEE 1588v2................................................................................................................................................3-24 Architecture....................................................................................................................................3-25 Transmit Datapath.........................................................................................................................3-26 Receive Datapath............................................................................................................................3-27 Frame Format.................................................................................................................................3-27 Configuration Registers...................................................................................... 4-1 Register Access Type Convention............................................................................................................. 4-1 Register Map.................................................................................................................................................4-2 Register Map (with and without Avalon-MM Adapter)........................................................................ 4-2 Primary MAC Address................................................................................................................................4-6 Transmit Configuration and Status Registers..........................................................................................4-7 Flow Control Registers..............................................................................................................................4-10 Unidirectional Control Register.............................................................................................................. 4-12 Receive Configuration and Status Registers...........................................................................................4-13 Transmit Timestamp Registers................................................................................................................4-20 Receive Timestamp Registers...................................................................................................................4-22 PMA Delay for IEEE 1588v2 MAC Registers.......................................................................................