SNS COLLEGE OF ENGINEERING Programmable Interrupt Controller (8259) The 8086 has only 2 interrupt line. If I/O devices need more interrupt line to transfer data, we go for Programmable Interrupt controllers. The Intel 8259 is a Programmable Interrupt Controller (PIC) designed for the Intel 8085 and Intel 8086 microprocessors. K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit -3 1 SNS COLLEGE OF ENGINEERING Important Features • In computing, a programmable interrupt controller (PIC) is a device that is used to combine several sources of interrupt onto one or more CPU lines, while allowing priority levels to be assigned to its interrupt outputs. K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING • PICs typically have a common set of registers: • Interrupt Request Register (IRR), • In-Service Register (ISR), • Interrupt Mask Register (IMR). • The IRR sores the interrupts request that is coming from 8 interrupt lines • The ISR register stores all the interrupts that are currently being serviced • The IMR stores the masking bits ie which interrupts are to be ignored and not acknowledged. K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Block Diagram K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Block Diagram Description • There are three registers, an Interrupt Mask Register (IMR), an Interrupt Request Register (IRR), and an In-Service Register (ISR). • Data bus buffer and read-write logic: are used to configure the internal registers of the chip. • Interrupt mast register (IMR): is used to enable or mask out the individual interrupt inputs through bits M0 to M7. 0= enable, 1= masked out. • Interrupt request register (IRR): is used to indicate all interrupt levels requesting service. K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Block Diagram Description • There are three registers, an Interrupt Mask Register (IMR), an Interrupt Request Register (IRR), and an In-Service Register (ISR). • Data bus buffer and read-write logic: are used to configure the internal registers of the chip. • Interrupt mast register (IMR): is used to enable or mask out the individual interrupt inputs through bits M0 to M7. 0= enable, 1= masked out. • Interrupt request register (IRR): is used to indicate all interrupt levels requesting service. K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Block Diagram Description • In service register (ISR): is used to store all interrupt levels which are currently being serviced. • Priority resolver: This block determines the priorities of the bits set in the IRR. • The highest priority is selected and strobed into the corresponding bit of the ISR during the INTA sequence. • Cascade-buffer comparator: Sends the address of the selected chip to the slaves in the master mode and decodes the status indicated by the master to find own address to respond. K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Block Diagram Description • One or more of the INTERRUPT REQUEST lines (IR0 - IR7) are raised high, setting the corresponding IRR bit(s). • The 82C59A evaluates those requests in the priority resolver and sends an interrupt (INT) to the CPU, if appropriate. • The CPU acknowledges the lNT and responds with an INTA pulse. • The 82C59 does not drive the data bus during the first INTA pulse. K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Block Diagram Description K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Signals of 8259 K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Signals of 8259 • Eight interrupt input request lines named IRQ0 through IRQ7, • An interrupt request output line named INTR, • Interrupt acknowledgment line named INTA, • D0 through D7 for communicating the interrupt level or vector offset. • Other connections include CAS0 through CAS2 for cascading between 8259s. K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Important Registers • The command words of 8259A are classified in two groups 1. Initialization command words (ICW) and 2. Operation command words (OCW) • Initialization Command Words (ICW): • Before it starts functioning, the 8259 must be initialized by writing two to four command words into the respective command word registers. • These are called as initialized command words K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Command word K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Command words of 8259 K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Command Words K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Command Words K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Command Words K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Command Words K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Modes of 8259 K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Modes of 8259 K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3 SNS COLLEGE OF ENGINEERING Modes of 8259 K.SANGEETHA/MPMC/I/O & MEMORY INTEFACING / unit - 3.