School of Electrical Engineering, Seoul National University SMDL Annual ’ 99 Design and Characterization of a Signal-Storage MOSFET-Controlled FEA Jung Hyun Nam ( [email protected] ) Abstract¦ ¡ Like TFT-LCD, active matrix driving scheme can be applied to FED and increase brightness by hundred times. Signal storage type pixels for AMFED are designed and made by using MOSFET-controlled FEA technology. Signal storing characteristics of the fabricated samples are measured. The samples are proven to store the input signal during enough time for active matrix driving. I. INTRODUCTION emitter array (MCFEA) in which a MOSFET is fabricated ost LCD driving schemes can be divided into active on a silicon substrate with FEA is already proven to be Mand passive matrix LCD(AMLCD and PMLCD) easily fabricated and reveal excellent characteristics in depending on whether each pixel has active devices like reliability, uniformity and driving voltage lowering[6,7]. thin film transistors (TFT) or not. Since AMLCD can The fabrication process techniques for MCFEAs can be fully use one frame time as optically active period by used to realize the active matrix FED in signal storage type storing the signals at the pixel site, it reveals hundreds times driving scheme. higher brightness and faster response than PMLCD. The The purpose of this paper is to report the design and pixel site signal storage of the active matrix scheme may be fabrication of the signal-storage MCFEA and the measured applicable to field emission display (FED). It will be a very characteristic of them, for the first time. promising concept for FED, but any reports on the perfect II. DESIGN AND FABRICATION implementation have rarely found yet. Because of the To drive field emitter arrays in passive addressing limitation of acceleration voltage applied to anode or scheme, X-Y addressing by row driver for horizontal line phosphor screen, FED has generally lower phosphor selection and column driver for pixel data driving is the brightness than CRT. With active matrix addressing, the basic method. Likely, for active matrix addressing, the brightness can be increased by about five hundred times for row driver selects a line and the column drivers generate VGA display at the same FEA emission current. analog signals to store at the pixel sites as shown in figure 1. Hashiguchi, et al. pointed out that the active matrix FED Each pixel includes an FEA, a low voltage MOSFET can be realized by using two transistors combined with a (LVMOS) for line selection and a high voltage MOSFET FEA[1]. (HVMOS) for controlling the emission current. A Unlike the case of PMLCD, some passive matrix FED capacitor is needed to store signal and this is composed of systems include active elements at the pixel site for low- the parasitic capacitor of connection line, the source region voltage pixel driving[2], emission current regulation[3], junction capacitor of LVMOS and the gate capacitor of protection from a short circuit between emitter and gate[4] HVMOS. and speeding up driving[5]. A MOSFET-controlled field ROW SHIFT REGISTER Field Emitter Array Storage DAC DAC DAC LVMOS Storage HVMOS Node COLUMN SHIFT REGISTER Figure 1. Schematic diagram of the signal-storage-type Figure 2. Physical layout of the designed signal-storage-type active matrix FED. Each field emitter tip symbol active matrix FED pixel. The area is 400´400 mm2 and a represents a FEA. FEA includes 25´25 field emission tips. School of Electrical Engineering, Seoul National University SMDL Annual ’ 99 100 V V DD 90 G,SEL 80 RDD 70 Gate Voltage = 5V A) 60 V 50 IN HVMOS LVMOS 40 4V Drain Current ( C 30 STG 20 3V 10 0V, 1V, 2V Figure 4. Circuit diagram for measuring the signal storage 0 0 10 20 30 40 50 characteristics of the signal-storage-type MCFEA pixel. Drain Voltage (V) The resistance of 200 kW is inserted to trace the transient (a) output current by oscilloscope. 100 100 90 Gate Voltage = 10 V Selection Gate Voltage = 18 V 90 80 16 V 9 V 80 70 A) 70 60 8 V A) 60 50 14 V 7 V 50 40 Drain Current ( 6 V 40 30 12 V 5 V Output Current ( 20 30 4 V 10 V 20 10 3 V 8 V 0V, 1V, 2V 0 10 0 10 20 30 40 50 60 70 80 90 6 V 0 Drain Voltage (V) 0 2 4 6 8 10 12 14 16 18 20 (b) Input Voltage (V) Figure 3. Measured I-V characteristics of the fabricated (a) low voltage and (b) high voltage MOSFET for MCFEA. Figure 5. Controlled output current characteristics. A FED and test patterns of signal-storage-type MCFEA sample. The controlled output current is measured at the pixels are designed. Figure 2 shows the layout of the resistor inserted between the drain bias and the drain of designed pixel. These may embody the real active matrix HVMOS. Figure 5 shows the measured output current FED. Samples are fabricated by the same process according to the input voltage and the selection gate voltage technology developed for MCFEAs[8]. The gate oxide in DC mode. The input voltage is transferred to the gate thickness is 1000Å for active region and 8000Å for drift of HVMOS with sufficiently high selection gate voltage region of HVMOS. The thin gate oxide for active region and the output current is proportional to square of input is to reduce back bias effect and enhance driving capability. voltage. But, when the input voltage increases over The field emitters are composed of gate holes shrunk to threshold voltage than the selection gate voltage, the about 1mm diameter by LOCOS process and molybdenum LVMOS goes into cut-off mode and the transferred voltage tips by well-known Spindt process. is fixed. Figure 6 shows the measured output current wave forms III. MEASUREMENT RESULTS after the selection gate turned off under three illumination Figure 3 shows the measured I-V characteristics of the conditions. When the selection gate gets turned off, the fabricated LVMOS and HVMOS. LVMOS can flow drain input voltage stored in storage capacitor decreases because current of over 50 mA with 5V of gate voltage and 20V of of the junction leakage current and optically generated drain voltage without any breakdown or punch through current under illumination. As shown in the figure, the phenomena. The measured threshold voltage and back output current sustains about 5 seconds, which is bias effect factor are 2.2 V and 2.1 V1/2, respectively. sufficiently long compared to the frame time of 1/60 s. HVMOS has drift region to reduce the drain edge field and With door opened the normal fluorescent light illuminate reveals higher breakdown voltage over 75V but the drain the sample and the output current decays in 10 ms. current level is lower under same bias condition. Another measurement reveals the optically generate current A test circuit is prepared as shown in figure 4 to measure is 270 pA at the storage node and the storage capacitor is the signal storage characteristics of the fabricated MCFEA calculated to be pF order. When the microscope light is School of Electrical Engineering, Seoul National University SMDL Annual ’ 99 Gate On Gate Off Gate On 35 20 Pulse Height Dark 30 18 8 VPP Door Opened 10 VPP 16 25 Light On 12 VPP 14 A) A) 20 12 Turned-on 10 Dark 15 Output Current ( 8 10 Output Current ( 6 Door Opened 5 4 Turned-off 0 2 Light On 0 1 2 3 4 5 6 7 8 0 Input Voltage (V) 0 5 10 15 20 25 (a) Time (ms) 7 (a) 20 18 6 Pulse Height Dark Light On 18 8 VPP 16 Turned-on 5 16 10 VPP 14 12 VPP 14 4 A) A) 12 12 10 3 10 8 8 2 Turned-off Floating Gate Voltage (V) Output Current ( 6 6 Output Current ( 1 4 4 2 2 0 0 1 2 3 4 5 6 7 8 0 0 Input Voltage (V) 0 2 4 6 8 0 100 200 Time (s) Time (ms) (b) (b) (c) Figure 7. (a)The measured output current levels and (b)the extracted floating node voltage when the gate is turned on Figure 6. The measured output current decaying and turned off in dark state. characteristics of (a)the fabricated circuit measured for 1/60 seconds under three different illumination conditions. (b) REFERENCE Long time and (c) short time measurements were also [1] G. Hashiguchi, H. Mimura, and H. Fujita, “A novel multi- performed to trace the dark and highly illuminated state layered device of polycrystalline silicon field emitters and decaying. thin film transistors for field emission displays,” Proc. Of IDW’ 96, pp.159-162, 1996. turned on over the sample, the generated current is 46 nA [2] S. L. Casper, T. A. Lowrey, “Flat panel display in which low- and the output decays in 100 ms. But the result include the voltage row and column address signals control a much RC time delay at the output node. higher pixel activation voltage,” United States Patent, No. As shown in figure 6, the output current abruptly drops 5210472, 1992. because of the capacitance coupling. This phenomenon is [3] T. Hirano, S. Kanemaru, and J. Itoh, “A MOSFET-Structured also well known in the TFT-LCD. Figure 7(a) shows the Si Tip for Stable Emission Current,” in IEDM’ 96 Tech. Dig., measured current level drops by gate pulse. From the pp. 309-312, 1996. results of the figure 5, the current level can be converted to [4] K.