1 A Simplification Method of Polymorphic Boolean Functions Wenjian Luo and Zhifang Li Abstract—Polymorphic circuits are a special kind of circuits adopted [4, 10, 11]. The evolutionary methods could design which possess multiple build-in functions, and these functions are area-efficient polymorphic circuits, but the Evolutionary activated by environment parameters, like temperature, light and Algorithms face the scalability problem. Therefore, only small VDD. The behavior of a polymorphic circuit can be described by scale circuits can be generated. Up to now, “3×4 multiplier / 7 a polymorphic Boolean function. For the first time, this brief presents a simplification method of the polymorphic Boolean bit sorting-net” reported in [4] is the biggest polymorphic function. circuits designed by evolutionary methods. In [12, 13], Sekanina and his colleagues proposed the Poly-BDD and Index Terms—Polymorphic electronics, polymorphic circuit, polymorphic multiplex methods for designing polymorphic polymorphic Boolean function, Karnaugh Map circuits. It is noted that polymorphic multiplex method is firstly proposed in [11], and also adopted in [14], but they are I. INTRODUCTION somewhat different. the In [15], the Poly_Bi_Decomposition ompared with the traditional electronics, the polymorphic method is proposed to synthesize polymorphic circuits. C electronic components possess multiple build-in functions The behavior of a polymorphic circuit can be described by a which are activated by environmental signals. For instance, polymorphic Boolean function. The simplification of a the AND/OR polymorphic logic gate controlled by Boolean function is common, and its importance stems from temperature perform the AND function when the temperature the fact that “the simpler the function is, the easier it is to is 27°C and perform the OR function when the temperature is realize” [16]. In this brief, a simplification method of 125°C [1]. Due to the multiple-functional and sensing polymorphic Boolean functions is given. It is shown that how properties, polymorphic electronics have several potential the proposed simplification rules are applied to minimize a applications in security, verification, multi-functional circuits polymorphic Boolean function through Karnaugh Map [16, and smart systems [2-4]. The possible applications of 17]. polymorphic electronics have been summarized in [1, 4] The rest of the paper is organized as follows. Section II Polymorphic gates are fundamental components of introduces the simplification method of polymorphic Boolean Polymorphic Electronics. They are basic building blocks of functions. Section III shows examples of the simplification, polymorphic circuits. In each working mode, a polymorphic and some guidelines are given for simplifying polymorphic gate would perform a different logic function. Some Boolean function on Karnaugh Map. Section IV gives some polymorphic gates have been designed and fabricated. In [5] discussion. Section V concludes this brief. and [6], two different NAND/NOR gate controlled by voltage are designed, and they are fabricated in silicon with 0.5 μm II. SIMPLIFICATION OF POLYMORPHIC BOOLEAN FUNCTIONS and 0.7 μm CMOS technology, respectively. Different In this section, firstly, the definitions of the polymorphic AND/OR gates, which are controlled by temperature and Karnaugh Map and the polymorphic cube are introduced. voltage, respectively, are designed in [1] and [7]. Secondly, the simplification rules of polymorphic Boolean NAND/NOR/NXOR/AND is reported in [8]. A reconfigurable functions are given, and it is shown that how these rules are polymorphic chip REPOMO32 is introduced in [9]. This applied in the polymorphic Karnaugh Map. REPOMO32 chip consists of 32 two-input elements which would performs the function AND, OR, XOR or NAND/NOR. A. The Polymorphic Karnaugh Map and Polymorphic Cube Polymorphic logic circuits are composed of polymorphic A polymorphic Boolean function f can be presented as f1/f2, logic gates. In each working mode, a polymorphic circuit where f1 and f2 are traditional Boolean functions. In mode 1, performs a traditional Boolean function. For example, a its function is f1, and in mode 2, its function is f2. Figure 1 polymorphic circuit “4-parity / 4-majority” would perform as shows the polymorphic Boolean function of 4-bit parity in the first mode, and perform as 4-majority in the “4-parity / 4-majority”. In mode 1, the function is 4 bit parity, second mode. and in mode 2, the function is 4 bit majority. Researchers have proposed some methods for synthesizing polymorphic circuits. Evolutionary methods are widely Wenjian Luo and Zhifang Li are with the Anhui Key Laboratory of Software in Computing and Communication, the School of Computer Science and Technology, University of Science and Technology of China, Hefei 230027, China (phone:86-551-3602824). Email: [email protected], [email protected]. 2 Fig. 1. The polymorphic Boolean function “4-parity / 4-majority” Boolean function. In Figure 4, c1 = c1,1/c1,2 and c2 = c2,1/c2,2 are A polymorphic Boolean function can be expressed in the two polymorphic subcubes, where c1,1 and c2,1 are the cubes in form of an Algebraic Expression. For example, the first mode, and c2,1 and c2,2 are the cubes in the second f = ((x2 AND/AND x3 ) XOR/OR x1 ) OR/OR x4 is the mode. The points in dashed part of the cubes have value 1, and algebraic expression of a polymorphic Boolean function. For the points in the white part of the cubes have value 0. P1 and convenience, it can be rewritten as P2 are the expression of characteristic function of c1 and c2, f = x2 x3 XOR/OR x1 + x4 . In the first mode, the function is respectively. ((x2 x3 ) ⊕ x1 ) + x4 , and in the second mode, the function is c1,1 c1,2 x3 x4 c2,1 c2,2 x1 x2 00 01 11 10 x2 x3 + x1 + x4 00 0/1 c1 Similar to the Karnaugh Map of traditional Boolean 01 0/1 function, a polymorphic Boolean function can be described by 0/1 1/0 0/1 0/1 c2 11 a polymorphic Karnaugh Map. Figure 2 illustrates the 10 0/1 (R1) P1 AND / XOR P2 polymorphic Karnaugh Map of “4-parity / 4-majority”. Each x1x2 AND/XOR x3 x4 square has four possible values, i.e. 0/0, 0/1, 1/0 and 1/1. x3 x4 x x 00 01 11 10 1 2 00 1/1 01 1/1 11 1/1 1/0 1/1 1/1 10 1/1 (R2) P1 OR / XOR P2 x1 x2 OR/XOR x3 x 4 x3 x4 x1 x2 00 01 11 10 00 0/1 01 0/1 Fig. 2. The polymorphic Karnaugh Map of “4-parity / 4-majority” 11 0/1 1/1 0/1 0/1 10 0/1 n (R3) P1 AND / OR P2 B (B∈{0, 1}) is a hypercube described by the Boolean x1 x2 AND/OR x3 x 4 variables x1, x2, …, xn. If each node of a hypercube is assigned x3 x4 00 01 11 10 a binary value (i.e. 0 or 1), this hypercube specifies a Boolean x1 x2 function. Similarly, if each node is assigned a polymorphic 00 1/0 value (i.e. 0/0, 0/1, 1/0 or 1/1), this hypercube specifies a 01 1/0 polymorphic Boolean function. Figure 3 is the cube 11 0/1 0/0 0/1 0/1 10 1/0 presentation of “4-parity / 4-majority”. (R4) P1 ANDNA / ANDNB P2 x1x2 ANDNA/ANDNB x3 x4 x3 x4 x x 00 01 11 10 c1,1 c1,2 1 2 00 c 1 01 1/1 1/1 11 1/1 1/1 10 (R5) P1 x2 x4 x3 x4 x1 x2 00 01 11 10 00 01 0/1 11 0/1 10 (R6) ZERO/P Fig. 3. The cube presentation of “4-parity / 4-majority” 1 x ZERO/AND x x 2 3 4 A m-dimentional subcube is of paramount importance in the Fig. 4. The basic simplification rules of polymorphic Boolean functions Boolean algebra. In fact, the characteristic function of a subcube (i.e. the points in the subcube are assigned value 1, In Figure 4(R1), if c1,1 ∩ c2,1 is 1-cube (i.e. all points in the and value 0 elsewhere) can be expressed as the product of cube have value 1, (c1,1 ∩ c2,1) - (c1,1 ∩ c2,1) is 0-cube, n - m variables. In the next section, based on the polymorphic c1,2 ∩ c2,2 is 0-cube and (c1,2 ∩ c2,2) - (c1,2 ∩ c2,2) is 1-cube, c1 cubes, the simplification rules of polymorphic Boolean and c2 can be expressed as “P1 AND/XOR P2”. In the right of function are given. Figure 4, examples are given to show how these rules are applied in polymorphic Karnaugh Map. B. The Simplification Rules In many cases, the minimization rules in Figure 4 are not Figure 4 gives the basic rules to minimize a polymorphic sufficient. For example, the instance in Figure 5(a) is a 3 modified version of the pattern in Figure 4(R1). Patterns in Figure 6(R7, R8), Figure 6(R9, R10), Figure 6(R11, R12) and Figure 5(b) and Figure 5(c) are often met in the simplification. Figure 6(R13, R14) are the extended versions of Figure 4(R1), However, they cannot be minimized. Figure 4(R2), Figure 4(R3) and Figure 4(R4), respectively. Therefore, the extended rules are given in Figure 6, where Figure 7(R15) and Figure 7(R16) solve the minimization of three polymorphic cubes are considered in the simplification. Figure 5(b) and Figure 5(c), respectively. c1,1 c1,2 x3 x4 c1,1 c1,2 x3 x4 c2,1 c2,2 x1 x2 00 01 11 10 c2,1 c2,2 x1 x2 00 01 11 10 00 0/1 00 0/1 c1 c1 01 0/1 01 0/1 0/1 1/0 0/1 0/1 0/1 0/1 0/1 0/1 c2 11 c2 11 10 1/0 10 0/1 (a) (b) c1,1 c1,2 x3 x4 c2,1 c2,2 x1 x2 00 01 11 10 00 0/1 c1 01 0/1 0/1 0/0 0/1 0/1 c2 11 10 0/1 (c) Fig.