IBM Haifa Leadership Seminar - Agenda IBM Verification Seminar 2004 November 21, 2004 9:15 Arrival 12:50 Piparazzi: A Micro-architecture Approach to Functional & Performance 9:30 Welcome, Verification in Processors, David Bernstein, Mgr., Software and Eyal Bin, IBM Haifa Labs Verification Technologies, IBM Haifa Labs 13:20 Lunch 9:45 Formal Verification of Synchronizers in GALS SoCs, 14:30 Keynote: Predicate Abstraction Ran Ginosar, Head, VLSI Systems and Refinement Techniques for Verifying Research Center, Electrical Engineering Verilog, Department, Technion - Israel Institute of Ed Clarke, FORE Systems Professor of Technology Computer Science and Professor of Electrical and Computer Engineering, 10:25 A Massively Parallel Platform for Carnegie Mellon University Formal Verification: RuleBase Parallel Edition, 15:30 Break Rachel Tzoref, IBM Haifa Labs 15:45 Debugging complex FPGA 10:55 SystemVerilog: Introduction and a platforms, User Perspective, Ivo Bolsens, Vice President and Chief Johny Srouji, Engineering Manager, Intel Technology Officer, Xilinx CAD Division, Haifa 16:15 Panel: HVL vs. HDVL, 11:25 Coffee break Panelists: Coby Chanoch, Verisity; Jay Lawrence, Cadence Design Systems; 11:40 State of the Technology Industry in Kobi Pines, Marvell Technology Group; Israel... and the Future, Rob Slater, FreeScale Semiconductor, Orna Berry, Venture Partner in Gemini Israel Funds and Former Chief Scientist of 17:00 Concluding Remarks, the Israeli Ministry of Industry and Trade Michael Rodeh, Director, IBM Haifa Labs 12:20 EDA Standards: Motivation, Players, Challenges, and Achievements, Dennis Brophy, Chair, Accellera Standards Organization and Director of Strategic Business Development, Model Technology http://www.haifa.il.ibm.com/Workshops/verification2004/.