External Memory Interface Handbook Volume 2: Design Guidelines Last updated for Altera Complete Design Suite: 15.0 Subscribe EMI_DG 101 Innovation Drive 2015.05.04 San Jose, CA 95134 Send Feedback www.altera.com TOC-2 Selecting Your Memory Contents Selecting Your Memory.......................................................................................1-1 DDR SDRAM Features............................................................................................................................... 1-2 DDR2 SDRAM Features............................................................................................................................. 1-3 DDR3 SDRAM Features............................................................................................................................. 1-3 QDR, QDR II, and QDR II+ SRAM Features..........................................................................................1-4 RLDRAM II and RLDRAM 3 Features.....................................................................................................1-4 LPDDR2 Features........................................................................................................................................ 1-6 Memory Selection........................................................................................................................................ 1-6 Example of High-Speed Memory in Embedded Processor....................................................................1-9 Example of High-Speed Memory in Telecom....................................................................................... 1-10 Document Revision History.....................................................................................................................1-11 Selecting Your FPGA Device...............................................................................2-1 Memory Standards.......................................................................................................................................2-1 I/O Interfaces................................................................................................................................................2-2 Wraparound Interfaces............................................................................................................................... 2-2 Read and Write Leveling.............................................................................................................................2-2 Dynamic OCT.............................................................................................................................................. 2-2 Device Settings Selection.............................................................................................................................2-3 Device Speed Grade......................................................................................................................... 2-3 Device Operating Temperature..................................................................................................... 2-3 Device Package Size......................................................................................................................... 2-3 Device Density and I/O Pin Counts..............................................................................................2-3 Document Revision History.......................................................................................................................2-5 Planning Pin and FPGA Resources.....................................................................3-1 Interface Pins................................................................................................................................................3-1 Estimating Pin Requirements.........................................................................................................3-4 DDR, DDR2, DDR3, and DDR4 SDRAM Clock Signals........................................................... 3-5 DDR, DDR2, DDR3, and DDR4 SDRAM Command and Address Signals........................... 3-5 DDR, DDR2, DDR3, and DDR4 SDRAM Data, Data Strobes, DM/DBI, and Optional ECC Signals................................................................................................................................. 3-6 DDR, DDR2, DDR3, and DDR4 SDRAM DIMM Options.......................................................3-8 QDR II, QDR II+, and QDR II+ Xtreme SRAM Clock Signals.............................................. 3-11 QDR II, QDR II+ and QDR II+ Xtreme SRAM Command Signals.......................................3-12 QDR II, QDR II+ and QDR II+ Xtreme SRAM Address Signals........................................... 3-12 QDR II, QDR II+ and QDR II+ Xtreme SRAM Data, BWS, and QVLD Signals.................3-12 QDR IV SRAM Clock Signals...................................................................................................... 3-13 QDR IV SRAM Commands and Addresses, AP, and AINV Signals..................................... 3-14 QDR IV SRAM Data, DINV, and QVLD Signals..................................................................... 3-14 RLDRAM II and RLDRAM 3 Clock Signals..............................................................................3-15 Altera Corporation Selecting Your Memory TOC-3 RLDRAM II and RLDRAM 3 Commands and Addresses.......................................................3-16 RLDRAM II and RLDRAM 3 Data, DM and QVLD Signals.................................................. 3-16 LPDDR2 Clock Signal................................................................................................................... 3-18 LPDDR2 Command and Address Signal................................................................................... 3-18 LPDDR2 Data, Data Strobe, and DM Signals............................................................................3-18 Maximum Number of Interfaces.................................................................................................3-18 OCT Support ................................................................................................................................. 3-30 Guidelines for Arria 10 External Memory Interface IP........................................................................3-31 General Pin-Out Guidelines for Arria 10 EMIF IP...................................................................3-32 Resource Sharing Guidelines for Arria 10 EMIF IP..................................................................3-35 Guidelines for UniPHY-based External Memory Interface IP............................................................3-37 General Pin-out Guidelines for UniPHY-based External Memory Interface IP.................. 3-37 Pin-out Rule Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II, Stratix III and Stratix IV Devices............................................................................3-38 Pin-out Rule Exceptions for RLDRAM II and RLDRAM 3 Interfaces.................................. 3-43 Pin-out Rule Exceptions for QDR II and QDR II+ SRAM Burst-length-of-two Interfaces................................................................................................................................... 3-45 Pin Connection Guidelines Tables..............................................................................................3-45 PLLs and Clock Networks............................................................................................................ 3-59 Using PLL Guidelines................................................................................................................................3-65 PLL Cascading............................................................................................................................................3-66 DLL.............................................................................................................................................................. 3-66 Other FPGA Resources............................................................................................................................. 3-67 Document Revision History.....................................................................................................................3-68 DDR2, DDR3, and DDR4 SDRAM Board Design Guidelines...........................4-1 Leveling and Dynamic ODT...................................................................................................................... 4-2 Read and Write Leveling.................................................................................................................4-3 Dynamic ODT..................................................................................................................................4-4 Dynamic OCT in Stratix III and Stratix IV Devices................................................................... 4-5 Dynamic OCT in Stratix V Devices...............................................................................................4-6 Board Termination for DDR2 SDRAM....................................................................................................4-6 External Parallel Termination........................................................................................................4-6 On-Chip Termination.....................................................................................................................4-7 Recommended Termination Schemes.........................................................................................