74 Annual Report 1999 CTI PET Systems Inc., Knoxville, TN, USA. In all Table 1 Main crystal properties measurements, a calibrated XP2020Q photomultiplier with radiant sensitivity of 83mA/W at 420nm, corre- LSO YSO sponding to the integral quantum efficiency of 0.20 22 for both crystals, and a Na radioactive y-source was Light output [phe/MeV] 3600±360 2900±300 used. The samples were coated with white PTFE (polytetrafluoroethylene) tape, an optical reflector of Energy resolution FWHM 13.910.4 good quality, and were glued by 3x3 mm face to the [%]for511keV 9.510.3 PMT with silicone oil. Detection efficiency for We demonstrate that detection system which com- energy threshold of 250 0.58 0.15 bine PMT and a new inorganic scintillator such as keV LSO:Ce can be successfully used in Positron Emission Timing resolution [ns] for Tomographs. Despite of the slightly lower, than for energy threshold of 450 472 - BGO fraction of events which interact photoelectri- keV cally, and the natural background activity, properties such as good spatial resolution, high signal-to-noise- This work was presented as oral contribution at ratio, and excellent count rate capability, makes LSO NATO Advanced Research Workshop, Krzyze, Po- scintillator superior to BGO for PET scanner. land 2-4 September 1999. YSO may be considered as an alternative, if the high light output of LSO is required (e.g. in order to " Institute for Nuclear Studies, PL 05-400 enable higher spatial resolution), and in cases when Owock/Swierk, Poland natural background of LSO is limiting factor. This is 2) Forschungszentrum Rossendorf, PF~510119, particularly important for low count rate applications. D-01314 Dresden, Germany 3.8 JTAG Accelerator Device for Alice Experiment at CERN by A.Chlopik, M.Burns0 PL0001505 There was an idea to use Boundary-Scan Test and/or chips using BST which are far away from the (BST) protocol for testing integrated devices mounted JTAG Controller. This operation needs two JTAG on detectors of Alice experiment at CERN. But host cycles. In the first cycle the testing data is sent to the computer which controls the test cycles and analyses DUT. received data is distant about 30 m from a detector and The test result data from DUT is received by Ac- using BST protocol for testing we can find problems celerator Board along with TMS and TCK signals with sending and receiving signals for long distances which are also sent back from DUT. And this data is at high speed. The problem occurs when the delay to written into the FIFO memory by the control of these get the TDO signal back to the controller approaches signals. There also exists the second FIFO memory Vi of a TCK period (see fig. 1). So the idea of building located on the board. It is read during the first cycle JTAG Accelerator device was to make possible the and its data is ignored. In the second cycle is read the use of BST for distance up to 50 meters or more with memory which was filled in the first cycle and second maximum speed of controller which is 25MHz memory is written with fake data. JTAG Accelerator Device enables to test boards data readout cable delay Fig. 1 Situation when cable delay causes unproper data readout DEPARTMENT OF NUCLEAR ELECTRONICS 75 The JTAG Accelerator Device consists of three boards. One of them is for receiving and transmitting ADAPTOR BOARD the Boundary Scan signals and converting them into le-pin JTAG cablo with single the LVDS levels and storing the data in FIFO mem- itied and differential signals (short) ory. Second board is a converter between JTAG and LVDS standards. And the third is an adaptor card which makes possible to send and receive differential ACCELERATOR BOARD data via cable connecting the Controller and Accel- erator Board. The block diagram of JTAG Accelerator Device is presented in fig. 2. 40-pln LVOS caw* There were built at CERN two prototypes of the (long> JTAG Accelerator Device. Each of them was tested using 50 m long twisted pair flat cable. The first one CONVERTERS BOARD was capable to work properly with 18 MHz frequency of TCK signal. In the second prototype was used faster version of Altera programmable logic device. It could work with full speed of JTAG Controller which Fig. 2 JTAG Accelerator Device block diagram. was 25 MHz. 3.9 Timing and Fast Control of the LHCb Experiment at CERN by Z.Guzik and A.Chfopik PL0001506 LHCb is a hadron collider experiment planned for Krakow IFJ group is involved in the project since running on LHC machine at CERN. The main purpose spring 1999. SINS P-6 Department is responsible for of this experiment is to search for new physics design and construction of part of the Outer Tracker through precise tests of the heavy flavor sector of the system. P-3 Department participates in designing Standard Model.The Warsaw group, together with some vital elements of the Data Acquisition System i,HC-i) IMut.ir BitUt muk WAI. new. .virus RICH rate* •Hi Mil/ Loch) liiiiiiJLLU 4U TB/s T Tito Irom-I nd MnlttpK WTN <H- M i •» GJVs rS rS rS rS aj'C Suh»l'«rnt G TS (SI'C Variable latency 1,2-10 IMS rvv ri'Ti Omtml Event Fitter (Vi IVV M«nlt(iriria Fig. 1 Overall structure of LHCb Data Acquisition System The overall structure of the Data Acquisition is interest. As may be seen from the figure initial data depicted in fig. 1. A bold circle marks the area of our rate is estimated to be about 40 TB/s what indicates.