HIGH LEVEL DESIGN METHODOLOGY FOR RECONFIGURABLE SYSTEMS A dissertation presented to the faculty of the Russ College of Engineering and Technology In partial fulfillment of the requirements for the degree Doctor of Philosophy Mingwei Ding November 2005 This dissertation entitled HIGH LEVEL DESIGN METHODOLOGY FOR RECONFIGURABLE SYSTEMS by Mingwei Ding has been approved for the School of Electrical Engineering and Computer Science and the Russ College of Engineering and Technology by Janusz Starzyk Professor of Electrical Engineering and Computer Science Dennis Irwin Dean, Russ College of Engineering and Technology Ding, Mingwei. Ph.D. November 2005. Electrical Engineering and Computer Sci- ence High Level Design Methodology for Reconfigurable Systems (147pp.) Director of Dissertation: Janusz Starzyk The rise of reconfigurable computing systems presents great challenges to tradi- tional electronic system design mainly due to the dynamic reconfigurability require- ments of these systems. At the same time, the chip capacity is growing at a faster pace than that of design productivity, bringing up the problem of a \productivity crisis." Thus, there is a strong demand in the microelectronic design industry for electronic design automation tools and design paradigms that will improve the design productivity and utilize the full power of reconfigurable architectures. This dissertation addresses these needs and includes research on high-level design methodology for reconfigurable systems and studies applications of such systems. Two ongoing projects | SOLAR and DRAW | which are dedicated to machine learning and next generation mobile station design, respectively, were selected as examples of reconfigurable system applications. First of all, a novel design methodology and design language, Unified Algorithmic Design Language (UADL), have been proposed and developed. UADL allows the designer to enter a high-level algorithmic description once and automatically gener- ate executable code in different target languages, such as Matlab and VHDL. The proposed UADL tool has been applied to the design process of both projects with about 2 to 3 times savings in code sizes of their algorithmic parts. Regarding the selected projects' needs, the following topics have been studied: optimum interconnection, reconfigurable routing, mapping of the Turbo decoder al- gorithm and dimensionality reduction. An optimum interconnection scheme has been derived and a novel pipeline structure has been devised to realize the reconfigurable routing with linear hardware costs. Dimensionality reduction is an indispensable step for an efficient learning, feature extraction, classification, and image/pattern process- ing. Two postmapping algorithms have been developed and tested against real world data. An important contribution of this dissertation is the proposed new design method- ology based on UADL. The UADL methodology provides a high-level, unified, tool- independent design interface for system designers, as Java has provided a platform independent programming language for software developers. It is my hope and desire that this design paradigm will gain such popularity as Java did. Approved: Janusz Starzyk Professor of Electrical Engineering and Computer Science To My Dear Parents Acknowledgments After five years in Athens, my doctoral study is about to end. It would be impos- sible for me to finish this task without the help from many. First of all, I would like to thank my advisor Dr. Starzyk whose guidance and supports are the key elements of this dissertation. Also I am grateful for his career advice as a friend. Secondly, I want to extend my sincere thanks to my committee members, Dr. Curtis, Dr. Dill, Dr. Matolak and Dr. Mohlenkamp for reviewing my dissertation and giving me many helpful comments. Special thanks go to Dr. Mohlenkamp who first introduced LATEX to me and financed me to overcome last difficult time of my study life. The same special gratitude goes to Mrs. Zofia Starzyk as well, who had offered many financial support to me and cooked many delicious food for our research group parties. I need to thank Steven Diehl for helping me out with the LATEX template. Also I would like to express my thanks to my group members | Haibo, Yinyin, Yue, Zhen and James. At the same time, I owe a big \thank you" to all my friends who made my stay in Athens an enjoyable one. Last but not least, I would like to thank my parents who have always been the primary source of support to me. As its best was bought only at the cost of great pain. Driven to the thorn, with no knowledge of the dying to come. But when we press the thorn to our breast, We know........ We understand..... And still......we do it. | Colleen McCullough 7 Table of Contents Abstract 3 Dedication 5 Acknowledgments 6 List of Figures 9 List of Tables 12 1 Introduction 13 1.1 Motivation . 13 1.2 Previous Works . 17 1.3 Current Projects . 19 1.3.1 SOLAR . 19 1.3.2 DRAW . 20 1.4 Objectives . 20 1.5 Outline . 22 2 Reconfigurable System Design Methodology 23 2.1 Managing System Complexity . 23 2.2 UADL Motivation . 24 2.3 UADL Structure . 28 2.4 Comparison with Other Languages . 36 2.5 FSM Examples . 37 3 SOLAR System Design | It's all about connections! 42 3.1 Introduction . 42 3.2 Input Selection and Weighting Scheme . 44 3.2.1 Random vs. Greedy . 45 3.2.2 Optimal and Binary Weighting Schemes . 47 3.2.3 Simulation Results . 51 3.3 Reconfigurable Routing Channel . 54 8 3.3.1 Pipeline Structure . 56 3.3.2 Data Flow Description . 58 3.3.3 Node Operations . 62 3.3.4 Simulation Results . 66 3.4 Application Example . 68 3.5 Contributions by UADL . 75 4 DRAW System Design 81 4.1 Introduction . 81 4.2 DRAW Structure . 82 4.3 UADL Contribution . 84 4.4 Design Example { Turbo Decoder . 91 4.4.1 Introduction . 91 4.4.2 Turbo Decoding Algorithm . 91 4.5 DRAW Implementation Cost . 95 4.6 UADL Contributions . 97 5 Dimensionality Reduction 100 5.1 Preprocessing . 100 5.2 Dimensionality Reduction and Postmapping . 101 5.3 Principles of Postmapping . 103 5.4 Linear Postmapping . 104 5.5 SVD Postmapping . 108 5.6 Example Applications . 110 5.7 Conclusion . 122 6 Conclusions and Future Work 123 6.1 Conclusions . 123 6.2 Original Contribution . 126 6.3 Future Work . 126 Bibliography 128 Appendix A UADL Construction and Visitor Pattern 140 Appendix B List of Acronyms 144 Appendix C Source Code Used in Dissertation 147 9 List of Figures 1.1 Flexibility vs. performance. 14 1.2 Widening design productivity gap. 16 2.1 A typical VLSI design flow. 26 2.2 Similarity between Java design flow and UADL design flow. 27 2.3 Traditional design flow. 28 2.4 UADL design flow. 29 2.5 EBNF specification of UADL. 30 2.6 UADL MUX code for target VHDL. 32 2.7 UADL MUX code for target Matlab. 33 2.8 Module interchanging and detailing procedures. 34 2.9 Language commonalities and differences. 35 2.10 Incompatibleness among current tools. 36 2.11 UADL framework unifies the user design platform. 37 2.12 FSM diagram of the comment filter. 39 2.13 FSM code UADL implementation. 40 2.14 Generated VHDL FSM code (partial). 41 3.1 SOLAR structure. 43 3.2 Classification rate with different selection strategies . 46 3.3 Model of weighted sum of noisy signals . 47 3.4 Pgain vs. dP in a binary weighted connection . 51 3.5 Pgain vs. dP at Pgain = 0 in a binary weighted connection . 52 3.6 Visualization of Hamming distances for noisy vectors . 53 3.7 A 31-neuron network topology . 54 3.8 Pipeline structure overview. 57 3.9 Same network with two connection configurations. 58 3.10 Column 1, cycle 0 to cycle L + Pk. 59 3.11 Column 1, cycle 2L to cycle 2L + Pk. 60 3.12 Column 1 and 2, cycle 3L to cycle 3L + Pk. 60 3.13 Timing diagram between column 1 and 2. 61 3.14 KCPSM assembly code fragment for reading. 62 3.15 Single node read/write structure. 63 10 3.16 Node implementing Lm(x) and Em(x) operations. 65 3.17 Comparison between modified sigmoid and sigmoid. 66 3.18 Node implementing Em(x) operation. 67 3.19 Single node read/write waveform. 67 3.20 Design area vs. network size. 68 3.21 4 7 array processing 4-feature Iris data. 69 3.22 4 ×7 array RTL schematic. 70 3.23 No×de RTL schematic. 71 3.24 One column RTL schematic. 72 3.25 One column RTL schematic (2). 73 3.26 4 7 array layout by Xilinx tools. 74 × 3.27 UADL code for one column design. 75 3.28 Generated VHDL code for one column design (partial). 76 3.29 Sample UADL testbench code. 78 3.30 Generated VHDL code from UADL testbench code (clock). 79 3.31 Generated VHDL code from UADL testbench code (reset). 79 3.32 Generated VHDL code from UADL testbench code (din,tin). 80 4.1 A block diagram of DRAP. 83 4.2 Crossbar implementation for 4-bit Barrel Shifter. 84 4.3 3 Stage logarithmic implementation for 7-bit Barrel Shifter. 85 4.4 UADL design flow with VHDL Matlab code auto-generation. 85 4.5 VHDL simulation results for one stage bypass/shift unit. 86 4.6 Matlab results for generated barrelshift.m code. 87 4.7 VHDL simulation results for 3-stage bypass/shift unit. 88 4.8 Matlab results for generated barrelshift3.m code. 88 4.9 Layout map for 3-stage Barrel Shifter. 90 4.10 PCCC encoder proposed by 3GPP. 92 4.11 Turbo decoder structure. 92 4.12 Datapath for α calculation. 93 4.13 Datapath for LLR (4 states).