CPRI v6.0 IP Core User Guide Last updated for Quartus Prime Design Suite: 17.0 IR3, 17.0, 17.0 Update 1, 17.0 Update 2 Subscribe UG-20008 101 Innovation Drive 2019.01.02 San Jose, CA 95134 Send Feedback www.altera.com TOC-2 CPRI v6.0 IP Core User Guide Contents About the CPRI v6.0 IP Core.............................................................................. 1-1 CPRI v6.0 IP Core Supported Features.....................................................................................................1-2 CPRI v6.0 IP Core Device Family and Speed Grade Support................................................................1-3 Device Family Support.................................................................................................................... 1-3 CPRI v6.0 IP Core Performance: Device and Transceiver Speed Grade Support................... 1-5 IP Core Verification..................................................................................................................................... 1-6 Resource Utilization for CPRI v6.0 IP Cores........................................................................................... 1-6 Release Information.....................................................................................................................................1-8 Getting Started with the CPRI v6.0 IP Core.......................................................2-1 Installation and Licensing...........................................................................................................................2-2 Generating CPRI v6.0 IP Cores..................................................................................................................2-3 CPRI v6.0 IP Core File Structure............................................................................................................... 2-3 CPRI v6.0 IP Core Parameters................................................................................................................... 2-7 Integrating Your IP Core in Your Design: Required External Blocks.................................................2-17 Adding the Transceiver TX PLL IP Core....................................................................................2-18 Adding the Reset Controller.........................................................................................................2-20 Adding the Transceiver Reconfiguration Controller.................................................................2-22 Adding the Off-Chip Clean-Up PLL........................................................................................... 2-22 Adding and Connecting the Single-Trip Delay Calibration Blocks........................................2-23 Simulating Intel FPGA IP Cores..............................................................................................................2-25 Understanding the Testbench...................................................................................................................2-26 Running the Testbench..............................................................................................................................2-26 Compiling the Full Design and Programming the FPGA....................................................................2-28 Functional Description........................................................................................3-1 Interfaces Overview..................................................................................................................................... 3-1 CPRI v6.0 IP Core Clocking Structure......................................................................................................3-3 Example CPRI v6.0 Clock Connections in Different Clocking Modes.................................... 3-8 CPRI v6.0 IP Core Reset Requirements..................................................................................................3-10 Start-Up Sequence Following Reset.........................................................................................................3-14 Start-Up Sequence Interface Signals............................................................................................3-15 AUX Interface.............................................................................................................................................3-18 AUX Interface Signals....................................................................................................................3-18 AUX Interface Synchronization................................................................................................... 3-26 Auxiliary Latency Cycles...............................................................................................................3-26 Direct Interface CPRI Frame Data Format.................................................................................3-28 Direct IQ Interface.....................................................................................................................................3-30 Ctrl_AxC Interface.....................................................................................................................................3-32 Direct Vendor Specific Access Interface................................................................................................. 3-34 Real-Time Vendor Specific Interface.......................................................................................................3-36 Altera Corporation CPRI v6.0 IP Core User Guide TOC-3 Direct HDLC Serial Interface...................................................................................................................3-38 Direct L1 Control and Status Interface................................................................................................... 3-40 L1 Debug Interface.....................................................................................................................................3-44 Media Independent Interface (MII) to External Ethernet Block.........................................................3-44 Gigabit Media Independent Interface (GMII) to External Ethernet Block........................................3-47 CPU Interface to CPRI v6.0 IP Core Registers...................................................................................... 3-49 CPU Interface Signals....................................................................................................................3-50 Accessing the Hyperframe Control Words.................................................................................3-51 Auto-Rate Negotiation.............................................................................................................................. 3-55 Extended Delay Measurement................................................................................................................. 3-56 Extended Delay Measurement for Soft Internal Buffers........................................................... 3-56 Extended Delay Measurement for Intel Stratix 10 Hard FIFOs...............................................3-58 Extended Delay Measurement Interface.....................................................................................3-59 Deterministic Latency and Delay Measurement and Calibration.......................................................3-59 Delay Measurement and Calibration Features...........................................................................3-60 Delay Requirements.......................................................................................................................3-60 Single-Hop Delay Measurement.................................................................................................. 3-61 Multi-Hop Delay Measurement................................................................................................... 3-64 Delay Calibration Features........................................................................................................... 3-64 CPRI v6.0 IP Core Transceiver and Transceiver Management Interfaces..........................................3-68 CPRI Link........................................................................................................................................3-68 Main Transceiver Clock and Reset Signals.................................................................................3-69 Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface.......3-70 Intel Arria 10 and Intel Stratix 10 Transceiver Reconfiguration Interface............................. 3-71 Interface to the External Reset Controller.................................................................................. 3-73 Interface to the External PLL........................................................................................................3-74 Transceiver Debug Interface.........................................................................................................3-74 Testing Features..........................................................................................................................................3-75 CPRI v6.0 IP Core Loopback Modes...........................................................................................3-75 CPRI v6.0 IP Core Self-Synchronization Feature......................................................................3-76 CPRI v6.0 IP Core Signals...................................................................................4-1