Safety Manual for TMS570LC4x Hercules ARM Safety MCUs User's Guide Literature Number: SPNU540A May 2014–Revised September 2016 Contents 1 Introduction ........................................................................................................................ 8 2 Hercules TMS570LC4x Product Overview.............................................................................. 10 2.1 Targeted Applications .................................................................................................. 11 2.2 Product Safety Constraints ............................................................................................ 12 3 Hercules Development Process for Management of Systematic Faults ..................................... 13 3.1 TI Standard MCU Automotive Development Process ............................................................. 14 3.2 TI MCU Automotive Legacy IEC 61508 Development Process .................................................. 15 3.3 Yogitech fRMethodology Development Process ................................................................... 15 3.4 Hercules Enhanced Safety Development Process................................................................. 15 4 Hercules Product Architecture for Management of Random Faults........................................... 18 4.1 Safe Island Philosophy and Architecture Partition to Support Safety Analysis (FMEA/FMEDA) ............ 18 4.2 Identification of Parts/Elements ....................................................................................... 19 4.3 Management of Family Variants ...................................................................................... 20 4.4 Operating States ........................................................................................................ 20 4.5 Management of Errors ................................................................................................. 22 5 System Integrator Recommendations ................................................................................... 23 5.1 System Integrator Activities ........................................................................................... 23 5.2 Hints for Performing Dependent/Common Cause Failure Analysis Including the Hercules MCU ........... 25 5.3 Hints for Improving Independence of Function/Co-Existence of Function When Using the Hercules MCU 25 5.4 Support for System Integrator Activities ............................................................................. 25 6 Brief Description of Elements .............................................................................................. 26 6.1 Power Supply ........................................................................................................... 26 6.2 Power Management Module (PMM) ................................................................................. 26 6.3 Clocks .................................................................................................................... 27 6.4 Reset ..................................................................................................................... 27 6.5 System Control Module ................................................................................................ 28 6.6 Error Signaling Module (ESM) ....................................................................................... 29 6.7 CPU Subsystem ........................................................................................................ 29 6.8 Primary Embedded Flash ............................................................................................. 31 6.9 Flash EEPROM Emulation (FEE) .................................................................................... 32 6.10 Primary Embedded SRAM ............................................................................................ 33 6.11 CPU Interconnect Subsystem......................................................................................... 34 6.12 Peripheral Interconnect Subsystem .................................................................................. 35 6.13 Peripheral Central Resource 1 (PCR1) .............................................................................. 35 6.14 Peripheral Central Resource 2 (PCR2) .............................................................................. 36 6.15 Peripheral Central Resource 3 (PCR3) .............................................................................. 36 6.16 EFuse Static Configuration ............................................................................................ 37 6.17 OTP Static Configuration .............................................................................................. 37 6.18 I/O Multiplexing Module (IOMM)...................................................................................... 38 6.19 Vectored Interrupt Module (VIM) ..................................................................................... 38 6.20 Real Time Interrupt (RTI) .............................................................................................. 39 2 Table of Contents SPNU540A–May 2014–Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated www.ti.com 6.21 Direct Memory Access (DMA) ........................................................................................ 40 6.22 High-End Timer (N2HET), HET Transfer Unit (HTU) .............................................................. 40 6.23 Multi-Buffered Analog-to-Digital Converter (MibADC) ............................................................. 42 6.24 Enhanced Pulse Width Modulators (ePWM) ........................................................................ 42 6.25 Enhanced Capture (eCAP) ............................................................................................ 43 6.26 Enhanced Quadrature Encoder Pulse (eQEP) ..................................................................... 44 6.27 Multi Buffered Serial Peripheral Interface (MibSPI) ................................................................ 44 6.28 Inter-Integrated Circuit (I2C) .......................................................................................... 45 6.29 Serial Communication Interface (SCI) ............................................................................... 46 6.30 Local Interconnect Network (LIN) .................................................................................... 46 6.31 Controller Area Network (DCAN) ..................................................................................... 47 6.32 FlexRay, FlexRay Transfer Unit (FTU) .............................................................................. 48 6.33 General-Purpose Input/Output (GIO) ................................................................................ 49 6.34 Ethernet .................................................................................................................. 50 6.35 External Memory Interface (EMIF) ................................................................................... 50 6.36 JTAG Debug, Trace, Calibration, and Test Access ................................................................ 51 6.37 Cortex-R5F Central Processing Unit (CPU) Debug and Trace ................................................... 51 6.38 Data Modification Module (DMM)..................................................................................... 52 6.39 RAM Trace Port Interface (RTP) ..................................................................................... 52 6.40 Parameter Overlay Module (POM) ................................................................................... 52 6.41 Error Profiling Controller (EPC) ....................................................................................... 53 6.42 Temperature Sensor ................................................................................................... 53 7 Brief Description of Diagnostics........................................................................................... 54 7.1 1oo2 Software Voting Using Secondary Free Running Counter ................................................. 54 7.2 Bit Error Detection ...................................................................................................... 54 7.3 Bit Multiplexing in FEE Memory Array ............................................................................... 54 7.4 Bit Multiplexing in Flash Memory Array.............................................................................. 54 7.5 Bit Multiplexing in Primary SRAM Memory Array................................................................... 54 7.6 Bit Multiplexing in Peripheral SRAM Memory Array................................................................ 54 7.7 CPU Illegal Operation and Instruction Trapping ................................................................... 55 7.8 Logic Built In Self-Test (LBIST) ...................................................................................... 55 7.9 Logic Built In Self-Test (LBIST) Auto-Coverage .................................................................... 56 7.10 CPU Lockstep Compare .............................................................................................. 56 7.11 VIM Lockstep Compare ............................................................................................... 56 7.12 Lockstep Comparator Self-Test......................................................................................