Systems I Datapath Design I Topics Sequential instruction execution cycle Instruction mapping to hardware Instruction decoding Overview How do we build a digital computer? Hardware building blocks: digital logic primitives Instruction set architecture: what HW must implement Principled approach Hardware designed to implement one instruction at a time Plus connect to next instruction Decompose each instruction into a series of steps Expect that most steps will be common to many instructions Extend design from there Overlap execution of multiple instructions (pipelining) Later in this course Parallel execution of many instructions In more advanced computer architecture course 2 Y86 Instruction Set Byte 0 1 2 3 4 5 nop 0 0 addl 6 0 halt 1 0 subl 6 1 rrmovl rA, rB 2 0 rA rB andl 6 2 irmovl V, rB 3 0 8 rB V xorl 6 3 rmmovl rA, D(rB) 4 0 rA rB D jmp 7 0 mrmovl D(rB), rA 5 0 rA rB D jle 7 1 OPl rA, rB 6 fn rA rB jl 7 2 jXX Dest 7 fn Dest je 7 3 call Dest 8 0 Dest jne 7 4 ret 9 0 jge 7 5 pushl rA A 0 rA 8 jg 7 6 popl rA B 0 rA 8 3 Building Blocks fun Combinational Logic A A = Compute Boolean functions of L U inputs B 0 Continuously respond to input changes MUX Operate on data and implement 1 control Storage Elements valA A srcA Store bits valW Register W file dstW Addressable memories valB B Non-addressable registers srcB Clock Loaded only as clock rises Clock 4 Hardware Control Language Very simple hardware description language Can only express limited aspects of hardware operation Parts we want to explore and modify Data Types bool: Boolean a, b, c, … int: words A, B, C, … Does not specify word size---bytes, 32-bit words, … Statements bool a = bool-expr ; int A = int-expr ; 5 HCL Operations Classify by type of value returned Boolean Expressions Logic Operations a && b, a || b, !a Word Comparisons A == B, A != B, A < B, A <= B, A >= B, A > B Set Membership A in { B, C, D } » Same as A == B || A == C || A == D Word Expressions Case expressions [ a : A; b : B; c : C ] Evaluate test expressions a, b, c, … in sequence Return word expression A, B, C, … for first successful test 6 newPC SEQ Hardware PC valE, valM Write back Structure valM State DataData memory Program counter register (PC) Memory memory Addr, Data Condition code register (CC) Register File valE Memories CC CC ALU Access same memory space Execute Bch ALU aluA, aluB Data: for reading/writing program data Instruction: for reading valA, valB instructions srcA, srcB dstA, dstB A B Decode RegisterRegisterM Instruction Flow filefile Instruction Flow E Read instruction at address icode ifun valP rA , rB specified by PC valC InstructionInstruction PC Process through stages Fetch memory incrementincrement Update program counter PC 7 newPC PC valE, valM SEQ Stages Write back valM Fetch DataData memory Read instruction from instruction Memory memory memory Addr, Data Decode valE Read program registers CC Execute Bch ALU Execute aluA, aluB Compute value or address Memory valA, valB srcA, srcB Read or write data dstA, dstB A B Decode RegisterRegisterM filefile Write Back E icode ifun valP rA , rB Write program registers valC InstructionInstruction PC PC Fetch memory incrementincrement Update program counter PC 8 Instruction Decoding Optional Optional 5 0 rA rB D icode ifun rA rB valC Instruction Format Instruction byte icode:ifun Optional register byte rA:rB Optional constant word valC 9 Executing Arith./Logical Operation OPl rA, rB 6 fn rA rB Fetch Memory Read 2 bytes Do nothing Decode Write back Read operand registers Update register Execute PC Update Perform operation Increment PC by 2 Set condition codes Why? 10 Stage Computation: Arith/Log. Ops OPl rA, rB icode:ifun ← M1[PC] Read instruction byte rA:rB ← M [PC+1] Read register byte Fetch 1 valP ← PC+2 Compute next PC valA ← R[rA] Read operand A Decode valB ← R[rB] Read operand B valE ← valB OP valA Perform ALU operation Execute Set CC Set condition code register Memory Write R[rB] ← valE Write back result back PC update PC ← valP Update PC Formulate instruction execution as sequence of simple steps Use same general form for all instructions 11 Executing rmmovl rmmovl rA, D(rB) 4 0 rA rB D Fetch Memory Read 6 bytes Write to memory Decode Write back Read operand registers Do nothing Execute PC Update Compute effective address Increment PC by 6 12 Stage Computation: rmmovl rmmovl rA, D(rB) icode:ifun ← M1[PC] Read instruction byte rA:rB ← M [PC+1] Read register byte Fetch 1 valC ← M4[PC+2] Read displacement D valP ← PC+6 Compute next PC valA ← R[rA] Read operand A Decode valB ← R[rB] Read operand B valE ← valB + valC Compute effective address Execute Memory M4[valE] ← valA Write value to memory Write back PC update PC ← valP Update PC Use ALU for address computation 13 Executing popl popl rA b 0 rA 8 Fetch Memory Read 2 bytes Read from old stack pointer Decode Write back Read stack pointer Update stack pointer Execute Write result to register Increment stack pointer by 4 PC Update Increment PC by 2 14 Stage Computation: popl popl rA icode:ifun ← M1[PC] Read instruction byte rA:rB ← M [PC+1] Read register byte Fetch 1 valP ← PC+2 Compute next PC valA ← R[%esp] Read stack pointer Decode valB ← R [%esp] Read stack pointer valE ← valB + 4 Increment stack pointer Execute Memory valM ← M4[valA] Read from stack Write R[%esp] ← valE Update stack pointer back R[rA] ← valM Write back result PC update PC ← valP Update PC Use ALU to increment stack pointer Must update two registers Popped value New stack pointer 15 Summary Today Sequential instruction execution cycle Instruction mapping to hardware Instruction decoding Next time Control flow instructions Hardware for sequential machine (SEQ) 16.