eZ80® Microprocessors eZ80190 Product Brief PB005207-1103 Product Block Diagram • 3.3 V±0.3V supply voltage with 5V tolerant inputs eZ80190 MPU • 100-pin LQFP package 8KB MACC with 1KB 32-Bit • Up to 50MHz clock speed SRAM Dual-Port SRAM GPIO • Operating Temperature: – Standard Temperature Range: 0ºC to +70ºC 6 PRT WDT – Extended Temperature Range: –40ºC to 4 CS + +105ºC 2 DMA 2 UZI ZDI WSG • ZiLOG Debug Interface (ZDI) General Description Features The eZ80190 device is a high-speed, optimized The eZ80190 microprocessor is a member of pipeline architecture microprocessor, operating at ® ZiLOG’s eZ80 product family. It offers the fol- 50MHz. It is the first in a line of new eZ80® -based lowing features: standard products targeted toward embedded Inter- • Single-cycle instruction fetch, high-performance net applications. ® 50MHz eZ80 CPU core The eZ80® CPU is one of the fastest 8-bit CPUs • 8KB high-speed data SRAM available today, executing code four times faster than a standard Z80 operating at the same clock • 16x16-bit Multiply and 40-bit Accumulate with speed. In addition, the eZ80190 device includes a 1KB dual-port SRAM high-performance Multiply-Accumulator, ideal for • 32 bits of General-Purpose I/O signal processing. • Six Counter/Timers with prescalers The eZ80® CPU can operate in Z80-compatible (64 KB) mode, or full 24-bit (16 MB) addressing • Watch-Dog Timer mode. Considering both the increased clock speed • Four Chip Selects with individual Wait State and processor efficiency, the eZ80® CPU’s pro- generators cessing power rivals the performance of 16-bit microprocessors. • 2-channel DMA controller • 2 Universal ZiLOG Interface (UZI) channels eZ80® CPU Core (I2C, SPI, UART) with built-in Baud Rate Gen- The eZ80® CPU core is an 8-bit microprocessor erator that performs in either a 16- or 24-bit addressing • Fixed-priority vectored interrupts (32 external, mode. 11 internal) The eZ80® CPU improves on the world-f amous • On-chip oscillator Z80 architecture. Like the Z80, it features dual bank registers for fast context switching. ZiLOG, Inc. • 532 Race Street • San Jose, CA 95126 • ZiLOG Customer Support • www.ZiLOG.com eZ80190 Product Brief 2 eZ80190 Peripherals CLK ÷ 4, CLK ÷ 8 and CLK ÷ 16. The timers’ two modes of operation are single-pass and continuous Memory count mode. The timer can be programmed to start, On-board memory consists of 8KBx8 general-pur- stop, restart to continue, or restart from an initial pose SRAM and 1KB x 8 dual-port SRAM for the value. Multiply-Accumulator. Both memories can be individually enabled or disabled and can be relo- Watch-Dog Timer cated to the top of any 64KB page. The Watch-Dog Timer (WDT) features four pro- grammable time-out periods: 218, 222, 225, 227 Multiply-Accumulator Clock Cycles. It allows the user to monitor the sta- The Multiply-Accumulator on the eZ80190 device tus of a time-out and generate a RESET or Non- performs DSP functions without incurring the Maskable Interrupt. overhead associated with a separate DSP. Chip Select/Wait State Generator Features include: There are four chip selects for external de vices. • A 16x16-bit multiplier feeds 32-bit product into Each chip select may be programed for either one input of the adder. The other input of the memory or I/O space. Each memory chip select adder is fed from one of two 40-bit accumula- can be individually programmed on a 64KB tors. boundary. The I/O chip selects can choose a 16- • Two dual-port RAMs called X and Y. One port byte section of I/O space. Each chip select may be of each RAM is 16-bit Read-Only and supplies programmed for up to seven wait states. one side of the multiplier. The second port is 8- Direct Memory Access Controller bit Read/Write RAM, and is connected to the The Direct Memory Access (DMA) controller can microprocessor bus. This connection allo ws be used for direct memory-to-memory data trans- RAM to simultaneously be part of the multipro- fers without CPU intervention. There are two cessor’s memory space and constitute the X and DMA channels, channel 0 and channel 1. Each Y banks of the Multiply-Accumulator. channel features independent registers. Transfers • A set of registers in the microprocessor's I/O can be either in burst mode or cycle-steal mode. space start the Multiply-Accumulator, determine Universal ZiLOG Interface when the Multiply-Accumulator completes a Each of the two Universal ZiLOG Interface (UZI) calculation, and retrieves the resulting accumu- devices contains three serial communication con- lation. Software can provide calculation param- troller blocks (SPI, UART, and I2C) along with eters to these registers. control registers and a Baud Rate Generator General Purpose Input/Output (BRG). Only one of the serial devices is acti ve at There are 32 bits of General Purpose Input or Out- any time. put (GPIO). All port signals can be individually • The Baud Rate Generator provides a lower fre- programmable in either the Input or Output mode quency clock from the system clock. This mod- of operation.The 32 port bits can be used as vec- ule consists of a 16-bit counter, two 8-bit tored interrupt sources. The pins can be set to rec- preload registers and associated decoding logic. ognize either level- or edge-triggered interrupts. • The UART module implements all the logic Programmable Reload Timers required to support asynchronous communica- The eZ80190 device features six Programmable tions. The module also contains 16-byte deep Reloadable Counter Timers (PRT). Each timer is a FIFOs for both transmit and receive. 16-bit down counter and offers a 4-bit clock pres- • The SPI is a synchronous interface allo wing caler with four selectable taps for CLK ÷ 2, several SPI-type devices to be interconnected. PB005207-1103 eZ80® Microprocessors eZ80190 Product Brief 3 The SPI may be configured as either a master or change registers, edit programs, and view status of a slave. internal registers. • The I2C operates in four modes: Master Trans- On-Chip Crystal Oscillator mitter, Master Receiver, Slave Transmitter , and The eZ80190 microprocessor features an on-chip Slave Receiver. crystal oscillator that supplies clocks to both the ® ZiLOG Debug Interface internal eZ80 CPU core and peripherals and to an The ZiLOG Debug Interface (ZDI) incorporates external pin. The clock circuitry uses three dedi- most of the functions of an In-Circuit Emulator on- cated pins: XIN. XOUT, and PHI. chip. ZDI allows the user to single step code, Pin Diagram RTS0 RI0 DCD0 DSR0 DTR0 SS0/CTS0 DD IN OUT DD A7 A6 A5 A4 A3 A2 A1 A0 PHI BUSREQ GND V P P P P P P P P BUSACK X X GND V PD7/ PD6/ PD5/ PD4/ PD3/ PD2/SCK0/ PD1/MOSI0/RxD0/SDA0 PD0/MISO0/TxD0/SCL0 75 TEST 90 80 76 MREQ 100 1 PC7/RI1 WR PC6/DCD1 RD PC5/DSR1 CS0 PC4/DTR1 CS1 70 PC3/SS1/CTS1 CS2 PC2/SCK1/RTS1 CS3 PC1/MOSI1/RxD1/SDA1 V DD PC0/MISO1/TxD1/SCL1 GND GND A0 10 V A1 DD PB7 A2 100-Pin LQFP PB6 A3 eZ80® CPU PB5 A4 PB4 A5 60 PB3 A6 PB2 A7 PB1 V DD PB0 GND ZDA A8 20 ZCL A9 RESET A10 IORQ A11 INSTRD A12 HALT A13 25 51 26 30 40 50 D0 D1 D2 D3 D4 D5 D6 D7 DD DD DD A14 A17 A18 A19 A20 A21 A22 A23 A15 A16 NMI V V V GND GND GND Figure 1. eZ80190 100-Pin LQFP Pin Configuration PB005207-1103 eZ80® Microprocessors eZ80190 Product Brief 4 Block Diagram 1K Byte MACC Dual-Port Multiply MACC Accumulator SRAM UZI BUSACK Universal ZiLOG Interface BUSREQ (2) INSTRD Bus Controller IORQ I2C MREQ SCL0/1 Serial RD Interface SDA0/1 (2) WR DATA[7:0] 8K Byte General HALT SCK0/1 SPI Purpose NMI Serial eZ80® SS0/1 SRAM Peripheral CPU RESET MISO0/1 Interface TEST (2) MOSI0/1 ZDI Two-Channel ZiLOG ZCL DMA Debug Interface ZDA ADDR[23:0] Controller CTS0/1 DCD0/1 Interrupt CS0 Chip Select Vector DSR0/1 UART [7:0] & CS1 Universal DTR0/1 Asynchronous Wait State Interrupt CS2 Receiver/ Generator Controller RI0/1 Transmitter CS3 (2) RTS0/1 DATA[7:0] RXD0/1 TXD0/1 ADDR[23:0] WDT GPIO Crystal Programmable Watch-Dog General Oscillator Reload Purpose & Timer I/O Port System Clock Timer/Counter (4) Generator (6) Φ IN X OUT X PA[7:0] PB[7:0] PC[7:0] PD[7:0] Figure 2. eZ80190 Block Diagram PB005207-1103 eZ80® Microprocessors eZ80190 Product Brief 5 Electrical Features Summary • eZ80® Development Platform • Power supply: 3.3V ± 300 mV • Embedded Internet Software Suite including TCP/IP stack • Standard temperature: 0ºC to 70ºC • Real Time Operating System • Extended temperature: –40ºC to +105ºC • C-Compiler Support Tools • ZiLOG Development Suite (ZDSII) including assembler, linker, debugger, and simulator The following development tools are available to program and debug the eZ80190 device: Related Products Other integrated devices of interest are: eZ80L92 20MHz and 50MHz eZ80® CPU, low-power modes, 24 bits GPIO, IrDA, 2 UART, I2C, SPI, 6 Counter Timers with I/O features, WDT, RTC, 4-channel CS, JTAG, ZDI. eZ80F92 20MHz eZ80® CPU, low-power modes, 128 KB +256B Flash, 8KB SRAM, 24 bits GPIO, IrDA, 2 UART, I2C, SPI, 6 Counter Timers with I/O features, WDT, RTC, 4-channel CS+WSG, JTAG, ZDI, PLL. eZ80F93 20MHz eZ80® CPU, low-power modes, 64 KB +256B Flash, 4KB SRAM, 24 bits GPIO, IrDA, 2 UART, I2C, SPI, 6 Counter Timers with I/O features, WDT, RTC, 4-channel CS+WSG, JTAG, ZDI.