TLCS-900 16/32 BIT MICROCONTROLLER TLCS-900 Family TOSHIBA TOSHIBA CES_16BIT_V1.2 * TLCS-900 CPU-CORE LINE UP R4400 R4600 64-bit R5900 R3900 32-bit R3000A R1900 TLCS-900/H2 16-bit 68000 ASSP TLCS-900/L1 TLCS-900/H 68HC000 TLCS-900/L TLCS-900 8-bit 68HC11 TLCS-870 Std/ X/ C TLCS-90 Z80 ASSP 68HC05 4-bit TLCS-47E/47/470470A ALLIANCETOSHIBA ORIGINAL ALLIANCE TOSHIBA CES_16BIT_V1.2 * TLCS-900 The Family Key Features •CPU-core : 16/32 Bit • High-speed processing, ➨ Min. inst. exec. time: ➨200ns (@10MHz) - TLCS-900,900/L ➨160ns (@12.5MHz) - TLCS-900/H,900/L1 ➨ 50ns ((@20MHz) - TLCS-900/H2 •Large linear address space (16M bytes) • Powerful instruction set ➨ Regular instruction sets and many addressing modes •Many bit-processing operations • Powerful real-time processing ➨ using register banks •High-speed data transfer using µDMA • For systems using both 8- and 16-bit buses ➨ dynamic bus sizing function TOSHIBA CES_16BIT_V1.2 * TLCS-900 CPU CORES TOSHIBA CES_16BIT_V1.2 * TLCS-900 The Road Map [MIPS] 4 times TLCS-900/H2 performance of TLCS-900/H 10 • High performance TLCS-900/H TLCS-900/L1 TLCS-900 * TLCS-900,900/L,900/H devices will be • Mnemonic TLCS-900/L object compatible with TLCS-900/H2 1 Compatible • Standard • Low Power Family. PERFORMANCE TLCS-90 Z80 • Upward Compatible 8-bit 16-bit 32-bit TOSHIBA CES_16BIT_V1.2 * TLCS-900 The Family Key Features ITEM H2 H & L1 Stand.& L Max. operating 20 MHz 12.5 MHz 10 MHz frequency (external) (@10 MHz) (@25 MHz) (@20 MHz) Min. instruction cycle 50 nsec 160 nsec 200 nsec time uDMA Speed 0,25 usec 0,64 usec 1,6 usec MULA instruction 0.6 usec 1.52 usec 3.1 usec Dynamic Bus Sizing 8/16/32 Bit 8/16 Bit TOSHIBA CES_16BIT_V1.2 * TLCS-900 LOW VOLTAGE OPERATION TOSHIBA CES_16BIT_V1.2 * TLCS-900 TLCS-900/L Low power consumption ICC [mA] TLCS-900 50 (TMP96CM40F) 1 40 2 30 TLCS-900/L Ta = 25 oC (TMP93CM40F) 20 10 (5V,20MHz) (5V,20MHz) (3V,12.5MHz) TOSHIBA CES_16BIT_V1.2 * TLCS-900 TLCS-900/L1 Low power consumption ICC [mA] 19 mA 1 (3V,16MHz, Ta = 25 oC) 20 3 15 1 6 mA 10 2 3 mA 5 TLCS-900/H TLCS-900/L1 TLCS-900/L1 0.6um 0.6 um 0.4 um TOSHIBA CES_16BIT_V1.2 * TLCS-900 Gear Power Consumption per Software Icc <TMP93CM40F> [mA] Vcc = 3 V Ta = 25 oC 10 Prescaler 8 Gear Ratio 12 1/1 3 fc 4 6 fc/16 4 fc/8 Selector 1/2 fc/4 2 1/4 fc/2 1/8 fc 1/16 4 6 8 10 12 14[MHz] fc TOSHIBA CES_16BIT_V1.2 * TLCS-900 TLCS-900/L : DUAL CLOCK SYSTEM Reset Reset Release Software IDLE NORMAL mode mode 1 (20MHz) or 2 Software Interrupt Clock Gear Release Software Software STOP mode Release Software IDLE SLOW mode 1 mode Software or 2 Interrupt (32kHz) TOSHIBA CES_16BIT_V1.2 * TLCS-900 The operation modes • TLCS-900/L : <TMP93CM40F> [mA] 4 types of Stand-by mode Vcc=3V ()Ta =25 C 10 Operation CPU A/D C Peripheral Oscillator mode I/O (Timer,SIO) 8 NORMAL oooo Normal RUN xooo Icc 6 RUN IDLE2 xxoo 4 IDLE1 xxxo IDLE2 STOP xxxx 2 IDLE1 o = operate STOP x = stop 4 6 8 10 12 14 [MHz] fc TOSHIBA CES_16BIT_V1.2 * TLCS-900 HIGH SPEED OPERATION TOSHIBA CES_16BIT_V1.2 * TLCS-900 TLCS-900/H Performance 2 x TLCS-900 • Dual bus Method{• 32 bit ALU • 4bit barrel Shifter Operand Size Instruction Improving Target 8bit 16bit 32bit Trasnfer Oper. TLCS-900 4 4 4 LD reg,reg 2 2 2 C-compiler TLCS-900/H Performance Arithmetic Oper. Improvement 4 4 7 reg,reg 2 2 2 MULA reg,reg 31 19 Filter Calculation Logical Oper. Graphical RLC 4,reg 14 14 16 Processing 4 4 4 Floating Point Operation < Comparison table of states > TOSHIBA CES_16BIT_V1.2 * TLCS-900 THE 32 BIT TLCS-900/H2 CSIC like RISC TOSHIBA CES_16BIT_V1.2 * TLCS-900 Core comparison “H” V “H2” CSIC like RISC High Performance with RISC Technology 900/H2 900/H Minimum Execution Instruction Time 50ns 160ns Internal Clock Frequency 20MHz 12.5MHz Clock Per Instruction 1 CPI 2 CPI Internal Data bus 32 16 External Data bus 32 16 Performance Ratio 4 1 TOSHIBA CES_16BIT_V1.2 * TLCS-900 CPU - CORE Architecture TOSHIBA CES_16BIT_V1.2 * TLCS-900 The register configuration (1) Maximum Mode • Optimum for systems with program capacity above 64K bytes ➨ Program counter: 32 bits (lower 24 bits are output as address bus) • Large capacity data space ➨ 16Mbyte addressing can be specified by any general-purpose register • 32-bit transfer / arithmetic can be executed by general-purpose register • High Speed image processing/address calculation,etc TOSHIBA CES_16BIT_V1.2 * TLCS-900 The register configuration (1) WA XWA WAWA BC XBC BCBC 4 BANKS DE XDE DEDE HL XHL HLHL XIX IX XIY IY XIZ IZ (For System Mode) XSP SP (For Normal Mode) F’ SR F MAXIMUM MODE PC Program & Data : 16 bits 16M 32 bits TOSHIBA CES_16BIT_V1.2 * TLCS-900 The register configuration (2) Minimum Mode • Optimum for systems with program capacity less than 64K bytes ➨ Program counter: 16 bits • Large number of bank registers ➨ 16 bits x 4 registers x 8 banks • Large data capacity ➨ Expandable up to 16M bytes ➨ Accessible to data area above 64K bytes using XIX, XIY, XIZ, XSP registers • Capable of addressing with WA, BC, DE, HL, registers. TOSHIBA CES_16BIT_V1.2 * TLCS-900 The register configuration (2) WAWA WAWA MINIMUM MODE WABC WAWABCBC Program : 64K WABCBCDE BCBCDEDE Data : 16M BCDEDEHL DEDEHLHL DEHLHL HLHL HL 8 BANKS XIX IX XIY IY XIZ IZ (For System Mode) XSP SP (For Normal Mode) F’ SR F PC 16 bits 32 bits TOSHIBA CES_16BIT_V1.2 * TLCS-900 Instruction set examples • Filter operation instruction – MULA: 16 Bits x 16 Bits/32 Bits-32Bits (3.1us @ 20MHz) (signed multiplication-addition arithmetic) – MINC: Modulo increment...For circulating buffer pointer increment (Increments lower n bit only. 1 <= n <= 16) – MDEC: Modulo decrement...For circulating buffer pointer decrement (Decrements lower n bit only. 1 <= n <= 16) • Logical operation instructions – AND/OR/XOR: And/or/exclusive-or of 8, 16, and 32 bits TOSHIBA CES_16BIT_V1.2 * TLCS-900 Instruction set examples continued....... • Bit operation instructions – BIT/SET/RES/CHG: Bit test/set/reset/invert – LDCF/STCF:and any given bit Transfer between carry flag – ANDCF: And of carry flag and any given bit – ORCF: Or of carry flag and any given bit – XORCF: Exclusive-or of carry flag and any given bit – BS1: Searches bit pattern for 1. TOSHIBA CES_16BIT_V1.2 * TLCS-900 High -Speed Processing Family 900 & 900/L 900/H & 900/H2 Function 10 MHz 900/L1 20 MHz 12.5 MHz Instruction LD r, #8 200ns 160 ns 50 ns 8-bit transfer LD XHL, xrr 400ns 160 ns 50 ns 32-bit transfer AND XHL, (mem) 400ns 320 ns 100 ns 16-bit operation ADD HL, rr 700ns 160 ns 50 ns 32-bit operation SET b, (mem) 800ns 560 ns 200 ns bit set MUL HL, #16 2.6µs 1.2 µs 450 ns 16 bits * 16 bits DIV XHL, #8 3.0µs 1.84 µs 650 ns 32 bits / 16 bits MULA rr 3.1µs 1.52 µs 600 ns 16*16 +32 bits CALL #24 1.2 µs 800 ns 200 ns Direct Call JP #24 700 ns 480 ns 100 ns Direct Jump TOSHIBA CES_16BIT_V1.2 * TLCS-900 The memory map 000000H Built-in I/O (n) 256 64k 16M 000080H byte byte byte 000100H Internal RAM (n n) (R) 008000H (-R) Reset//Interrupt entry (R+) 008200H (R+d) (8100H Internal ROM (R+R) 900/L) (n n n) 010000H 900/L 256 byte reserved FFFFFFH TOSHIBA CES_16BIT_V1.2 * TLCS-900 The Interrupt (1) • Priority level (0 to 7) can be set for each interrupt source. • Non-maskable interrupts – Software interrupts (SWI0 to 7) – NMI pins – Watchdog timer – Privileged or undefined instruction violation • Maskable interrupts – External pins (INT 0,1,2,..) – Internal I/Os: DMA – Timer – SIO – A/D converter TOSHIBA CES_16BIT_V1.2 * TLCS-900 High-speed µDMA • DMA implemented using CPU block executed directly from microcode • Speed equivalent to DMA controller – 1- 2- byte transfer: • 1.6us (@20MHz) TLCS-900,900/L • 640ns (@25MHz) TLCS-900/H • Supports 4-channels, 16Mbyte address space • Maximum number of transfer blocks: 64k words • Many transfer modes: – 1) I/O to memory : (R+ bytes – 2) I/O to memory : (R- bytes – 3) memory to I/O : (R) bytes – 4) memory to I/O : (R) bytes – 5) I/O to I/O :TOSHIBA (R) CES_16BIT_V1.2 * bytes TLCS-900 The Interrupt (2) - Push PC, Interrupt - PUSHSR - SR<IFF2~0> > Data transfer accept int level +1 uDMA - SR<SYM> =1 Read interrupt vector clear interrupt request F/F PC=V+8000H Count = count-1 Interrupt service routine YES NO uDMA start Vector match RETI YES (POP SR) Count = 0 POP PC) NO END TOSHIBA CES_16BIT_V1.2 * TLCS-900 PERIPHERALS TOSHIBA CES_16BIT_V1.2 * TLCS-900 The Peripherals ROM/ Bus OTP/FLASH CPU Core Controller Interrupt Clock Oscillator/ Display RAM Controller Gear Dual Clock driver 16 Bit Watchdog 8 Bit Timers DMA DRAM J-TAG Timer Timers (Capture / Controller Controller Interface Compare) Stepper Chip UART 10-Bit D/A Motor / Select/ I2C Bus A/D CAN* Converter Pattern Wait Interface Converter Generator Controller I/O Ports * Under Development TOSHIBA CES_16BIT_V1.2 * TLCS-900 The chip select image /CS0 /CS1 /CS2 000000H 7F00H B0C1,0=“00” B1C1,0=“00” 8000H B2C1,0=“00” 400000H B0C1,0=“01” B1C1,0=“01” B2C1,0=“01” 800000H B0C1,0=“10” B1C1,0=“10” B2C1,0=“10” C00000H B0C1,0=“11” B1C1,0=“11” B2C1,0=“11” FFFFFFH TOSHIBA CES_16BIT_V1.2 * TLCS-900 The Prescaler Example of cycle at 20MHZ T0 T1 T2 T4 T8 T16 T32 T256 T1 (8/fc) 0.4 µsec T256 (2048/fc) 102.4µsec 0 1 2 3 4 5 6 7 8 Oscillator 1/4 9 bit prescalor circuit o1 1/2 System Clock o2 } PWM prescaler 0 1 2 3 4 Example of PWM cycle at 20MHz P1 (4/fc) 200ns P16 (64/fc) 3.2µsec P1 P4 P16 TOSHIBA CES_16BIT_V1.2 * TLCS-900 8 Bit Timer By cascading two 8-bit timers, a 16-bit timer can be configured.