EEB531 Microprocessor Systems 4-1 MOV Revisited 微處理機系統 • Data movement instructions – movement instructions: MOV, MOVSX, MOVZX, PUSH, POP, BSWAP, XCHG, XLAT, IN, OUT, LEA – string instructions: MOVS, LODS, STOS, INS, and OUTS – CMOV (conditional move) instruction on Pentium Pro – P4 More commonly used in programs • Assembler program: generate machine language – many variants: syntax and directives 吳俊興 • Microsoft MACRO assembler (MASM) • Intel Assembler (ASM) 高雄大學 資訊工程學系 • Borland Turbo assembler (TASM) – generate native binary code April 2005 3 Outline Instruction Formats 4-1 MOV Revisited 4-2 PUSH/POP 4-3 Load-Effective Address 4-4 String Data Transfers 4-5 Miscellaneous Data Transfers 4-6 Segment Override Prefix Override prefixes: first 2 bytes of 32-bit format 4-7 Assembler Detail – address-size prefix (67H): modify size of operand address – register-size prefix (66H): modify register size Not always present 2 4 Register-size Prefixes Byte 2 : MOD + REG + R/M • Default size MOD(mode), REG(register) and R/M(register/memory) – 16-bit instruction mode (either real or protected mode) uses • MOD: specify the addressing mode 8- and 16-bit register and addressing modes by default • All 8-bit displacements are sign-extended into – 32-bit instruction mode (protected mode only) uses 16-bit displacements (length=2 bytes) 8- and 32-bit register and addressing modes by default 00H-7FH (positive) → 0000H-007FH • Toggle register size 80H-FFH (negative) → FF80H-FFFFH – operate in 16-bit instruction mode and • a 16-bit register is used ⇒ register-size prefix is absent • a 32-bit register is used ⇒ register-size prefix (66H) is appended – operate in 32-bit instruction mode and • REG and R/M • a 32-bit register is used register assignments ⇒ register-size prefix is absent • a 16-bit register is used ⇒ register-size prefix (66H) is appended 5 7 Byte 1 : The Opcode Figure 4-4: MOV BP, SP (=8BEC) • Opcode: selects the operation performed by the µP – 1 or 2 bytes long for most (not all) machine instructions – addition, subtraction, move, and so on • Direction (D) of data flow – D=0: REG field → R/M field – D=1: REG field ← R/M field • Word (W) flag: whether the data are a byte or others – W=0: byte References –W=1: • below 80386 (16-bit instruction mode): word • In 80386 and above (32-bit instruction or protected mode) : – word (if with register-size prefix, 66H) – double word (if no register-size prefix) 6 8 16-bit R/M Memory-Addressing Modes Figure 4-6: MOV [1000H], DL (=88160040H) •MOD≠ 11 – MOD=00, and R/M=101 •[DI] – MOD=01 or 10, and R/M=101 • [DI + displacement] • Special addressing mode: only a displacement – MOD=00 and R/M=110 (no displacement and SS:[BP]*) since we cannot use addressing mode [BP] without a displacement 9 11 Figure 4-5: MOV DL, [DI] (=8A15) Figure 4-7: MOV [BP], DL (=885600H) References 10 12 32-bit Addressing Mode Segment MOV Instructions • 32-bit instruction mode, or 16-bit instruction mode by • a special set of register bits using address-size prefix 67H (REG) selects the segment • Example: 80386 and above register operated in the 16-bit instruction MOV EAX, [EBX+4*ECX] = 67 66 8B 04 8B H 67H: address size 66H: register size • Figure 4-10: MOV BX, CS (8C CBH) 8BH: opcode=100010, D=1, W=1 04H: MOD=00, REG=000, R/M=100 8BH: ss=10, index=001, Base=011 index and base both contain register numbers 13 15 Immediate instruction 4-2 PUSH/POP • Figure 4-9: MOV WORD PTR [BX+1000H], 1234H • store and retrieve data from the LIFO stack memory • 6 forms of PUSH/POP: register, memory, immediate, segment register, flags, and all registers – PUSH/POP immediate and PUSHA/POPA (all registers) are available to 80286 – Pentium 4 – PUSHAD/POPAD 32-bit register set are available to 80386 – Pentium 4 14 16 PUSH Registers PUSHA • PUSH AX on ESP and stack at 37FFH and 37FEH • SS[SP-1]=AH, SS[SP-2]=AL • SP = SP - 2 17 19 PUSH Immediate POP • performing inverse operation of a PUSH instruction • Two opcodes – no immediate POP – PUSH 8-/16-bit number – POPF / POPFD: pop flags • Opcode = 6AH for 00H-FFH – POPA / POPAD: pop all registers (reverse order of PUSHA) • Opcode = 68H for 0100H-FFFFH • removing data from the stack – PUSHD 32-bit number •Examples – 6A 08 H PUSH 8 – 68 00 10 H PUSH 1000H – 6A 41 H PUSH ‘A’ 18 20 Figure 4-13: POP BX 4-3 Load-Effective Address • LEA (Load-Effective Address): loads a 16- or 32-bit register with the offset address of the data – LEA BX, [DI] load the offset address specified by [DI] = MOV BX, DI – MOV BX, [DI] load the data stored at [DI] – LEA BX, LIST = MOV BX, OFFSET LIST 21 23 Initializing the Stack 4-4 String Data Transfer • If stack is to reside in memory 10000H – 1FFFFH • Five string data transfer instructions: LODS, STOS, MOVS, INS, – load SS with 1000H and OUTS – load SP with 0000H • Direction flag (D): auto-increment (D=0) or auto-decrement (DI) • If residing in memory 10000H – 10FFFH operation for DI and SI during string operations – load SP with 1000H – CLD: clear D flag (D=0) – STD: set D flag (D=1) • LODS: loads AL, AX or EAX with data stored at DI register • STOS: stores L, AX or EAX Figure 4-14 PUSH CX: cyclical nature of stack 22 24 Summary Chapter 4 Data Movement Instructions 4-1 MOV Revisited 4-2 PUSH/POP 4-3 Load-Effective Address 4-4 String Data Transfers 4-5 Miscellaneous Data Transfers 4-6 Segment Override Prefix 4-7 Assembler Detail 25.