Power Performance of IGZO DRAM memory A Thesis Presented to the Faculty of the School of Engineering and Applied Science University of Virginia In Partial Fulfillment of the requirements for the Degree Master of Science (Electrical Engineering) by Mandi Das May, 2019 APPROVAL SHEET This Thesis is submitted in partial fulfillment of the requirements for the degree of Master of Science Author Signature: This Thesis has been read and approved by the examining committee: Advisor: Mircea R. Stan Committee Member: Kyusang Lee Committee Member: Steven M. Bowers Committee Member: Committee Member: Committee Member: Accepted for the School of Engineering and Applied Science: Craig H. Benson, School of Engineering and Applied Science May 2019 ○c Copyright by Mandi Das 2019 Abstract C-axis aligned crystal In-Ga-Zn-oxide (CAAC-IGZO) is a novel crystal morphology discovered by Semiconductor Energy Laboratory which is different from other single- crystal, poly-crystalline and amorphous morphologies. It is neither single-crystal or amorphous with no clear distinct grain boundary making this material viable candi- date for thin film transistor. One particular property of interest is its high current-on to current-off ratio which enables extremely low power consumption and can be imple- mented as a virtual non-volatile memory for emerging memory technologies. In this thesis we work on a design strategy to replace SRAM with the IGZO 1T1C DRAM memory cell as last-level on-chip cache for microprocessors and study both the circuit level simulation and power performance at the system level. i Acknowledgments I would like to thank Dr. Mircea R. Stan for providing me with an opportunity to work on this fascinating project. I am able to reach this point because of his tremendous support and guidance. I’ll cherish the experiences and memories I had during my stay at UVA. I’m thankful for the honourable presence of my committee members (Dr. Mircea R. Stan, Dr. Steven M. Bowers, Dr. Kyusang Lee) for making my defense a wonderful experience and shaping me as a researcher and engineer. Lastly, I would like to thank my fellow members of HPLP who have always sup- ported and motivated me as a friend. ii Contents 1 Introduction1 1.1 Motivation.................................2 1.2 Contribution................................3 1.3 Organization...............................3 2 Background Information4 2.1 Memory..................................4 2.2 SRAM...................................5 2.3 DRAM...................................6 2.4 Flash memory...............................6 2.5 CAAC-IGZO...............................7 2.6 Retention Latch..............................8 2.7 NOSRAM and DOSRAM........................ 10 2.7.1 NOSRAM............................. 10 2.7.2 DOSRAM............................. 11 2.8 Summary................................. 14 3 Circuit analysis 15 3.1 Device model............................... 15 3.2 Circuit implementation of the device model............... 15 3.3 Results................................... 17 4 Cache Architecture Study 19 iii 4.1 CACTI................................... 19 4.2 Implementation.............................. 19 4.3 Results................................... 22 5 Multi-core Full-system simulation 24 5.1 GEM5................................... 24 5.2 Implementation.............................. 24 5.3 Benchmark................................ 26 5.4 McPAT.................................. 27 5.5 Implementation.............................. 28 5.6 Power model analysis........................... 28 6 Conclusion 31 7 Future Works 32 iv List of Figures 2-1 Memory Hierarchy [4]...........................4 2-2 A six-transistor CMOS SRAM cell...................5 2-3 1T1C DRAM cell.............................6 2-4 CAAC morphology [13]..........................7 2-5 Stacked structure of OS FET and Si FET [5]..............8 2-6 I-V characteristics of CAAC-IGZO and Si transistors [1].......8 2-7 I-V curve of IGZO below subthreshold [1]................9 2-8 Typical latch to latch Synchronous design................9 2-9 Retention latch with 1T1C backup IGZO element............ 10 2-10 1T1C circuit for the backup element................... 10 2-11 Retention period for various values of Vg [1].............. 11 2-12 (a) Circuit diagram. (b) Cross-sectional view. [5]........... 12 2-13 SRAM with IGZO back-up circuit [13]................. 12 2-14 Topology of the SRAM memory cell with backup circuit [13]..... 13 2-15 1T1C IGZO DRAM [13]......................... 13 2-16 (a) Without stack structure. (b) With the stack structure. [11].... 13 3-1 IGZO DUT for simulations [13]..................... 16 3-2 I-V graph of the IGZO verilog-a model.................. 16 4-1 Cache model used in CACTI [14].................... 20 5-1 A system configuration with a two-level cache hierarchy[8]...... 25 5-2 Mobile full-system structure [9]..................... 26 v 5-3 Block diagram of the McPAT framework [6]............... 28 5-4 Implementing to the McPAT framework................. 29 5-5 Power components during sleep...................... 29 5-6 Power components during active..................... 30 vi List of Tables 3.1 Retention period calculation with C = 10fF.............. 17 3.2 Retention period calculation with C = 1fF............... 17 3.3 Retention period calculation with C = 0.2fF.............. 17 4.1 IGZO-FET parameters for CACTI................... 21 4.2 Cache organization parameters...................... 22 4.3 Timing and power for different memory types............. 22 4.4 Timing and refresh power........................ 23 5.1 Mobile full-system configuration [9]................... 27 vii Chapter 1 Introduction With emerging technologies, scaling down devices to nanotechnology made its way to handheld high performance gadgets. Today majority of the global population are accessing internet service and many of them are connected through battery operated devices. A 2015 GlobalWebIndex survey showed that 80% of internet users own a smartphone, almost half own a tablet, and the majority of these almost two trillion mobile devices run the Android Operating System. Consumer devices, which include smartphones, tablets and wearables, have seen a tremendous growth in the last decade because of portability and performance. For this class of devices, energy efficiency is a first-class concern due to the limited battery capacity and thermal power budget. We find that data movement is a major contributor to the total system energy and execution time in consumer devices. The energy and performance costs of moving data between the memory system and the compute units are significantly higher than the costs of computation. Designing low power consuming devices are of foremost challenges in current technologies. In modern SOCs, the major component that consumes most of the power and area are the on-chip cache memories. SRAM consume a lot of power due to both static and dynamic power dissipation. DRAM additionally needs to refresh the data because of the degrading storage capacitor. There has been active research going on for non-volatile memories and have the advantage in terms of low-voltage operation and high-speed data writing and reading. But these memories have limited endurance 1 and low on/off ratio. Semiconductor Energy Laboratory developed a new crystal structure for oxide semiconductor known as C-Axis Aligned Crystalline In-Ga-Zn Oxide thin-film tran- sistor (CAAC-IGZO TFT) [5]. This device has very low parasitic leakages and low channel leakage. Because of the nature of the crystalline structure, there is no distinct boundary in the junction, making it a high endurance device. And since it has very low leakage, it can be designed to be used as a nonvolatile memory. In this thesis, we study the structures of Nonvolatile Oxide Semiconductor Ran- dom Access Memory (NOSRAM) [5] and Dynamic Oxide Semiconductor Random Access Memory (DOSRAM) [1]. Evaluate the parameters of the CAAC-IGZO FET that would enable us to select the feasible type of memory and hours of retention period. And then use open-source tools: CACTI, gem5 and McPAT, to study the timing and power savings using the IGZO device as cache memory. 1.1 Motivation Dynamic Random Access Memory is a volatile memory which needs to be peri- odically refreshed (typically 64ms [12]) to retain the data in the storage element. If not refreshed, the data is lost from the storage element because of the leakages of the access transistor to the stored bit. This frequent refresh of data is a source of power consumption in DRAM. CAAC-IGZO TFT has very low off-state current making it an extremely low-leakage device. This device can be used to replace the access tran- sistor in a bit cell that requires a larger refresh period, thereby reducing the power consumption of DRAM memory. 2 1.2 Contribution ∙ HSPICE was used to simulate the IGZO-TFT verilog-a model and evaluate the optimum range of operating voltage with low static power dissipation. ∙ Implementing the IGZO-DRAM as last-level cache memory in a full-system architecture to evaluate the timing and the power performance. 1.3 Organization The rest of the thesis is organized as follows: ∙ Chapter 2 provides the background information of different memory types and the motivation to use IGZO based memory. ∙ Chapter 3 studies the characteristics of the IGZO verilog-a model using HSPICE and find the range of operating voltage for longer retention period. ∙ Chapter 4 implements the cache structure with the IGZO-DRAM as last-level cache