See all versions of this document Vivado Design Suite User Guide Designing IP Subsystems Using IP Integrator UG994 (v2020.1) June 3, 2020 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 06/03/2020 Version 2020.1 General Updated for version 2020.1. Working with Presets to Control Block Design Views Added Addressing view. Chapter 3: Addressing for Block Designs Updated with new Address Editor feature, and renamed chapter. Using Bus Interfaces Added a link to UG1118 for more information about creating new interface definitions. Limitations of Selectively Upgrading IP in Block Designs Added two IP to the list of IP that must be upgraded when migrating from an older release of Vivado. UG994 (v2020.1) June 3, 2020 Send Feedback www.xilinx.com Designing IP Subsystems Using IP Integrator 2 Table of Contents Revision History...............................................................................................................2 Chapter 1: Getting Started with Vivado IP Integrator.............................. 6 Chapter 2: Creating a Block Design......................................................................7 Creating a Project........................................................................................................................7 Creating a Block Design..............................................................................................................9 Designing with IP Integrator................................................................................................... 12 Working with Presets to Control Block Design Views...........................................................55 Hierarchical IP in IP Integrator................................................................................................61 InterConnect vs. SmartConnect.............................................................................................. 66 Glue Logic IP in IP Integrator.................................................................................................. 68 About On-Disk Objects and In-Memory Objects................................................................... 73 Running Design Rule Checks................................................................................................... 75 Finding Objects in a Block Design...........................................................................................77 Chapter 3: Addressing for Block Designs........................................................ 81 Addressing Overview................................................................................................................ 81 Addressing Structure................................................................................................................ 81 Concepts.....................................................................................................................................82 Using the Address Editor..........................................................................................................83 Address Path Property View.....................................................................................................90 Block Diagram Addressing View..............................................................................................92 Cross probing with Address Editor......................................................................................... 93 Common Addressing-Related Critical Warnings and Errors................................................95 Chapter 4: Working with Block Designs...........................................................97 Generating Output Products................................................................................................... 97 Integrating the Block Design into a Top-Level Design....................................................... 105 Adding Existing Block Designs ............................................................................................. 108 Revision Control for Block Designs....................................................................................... 112 Exporting a Hardware Definition to Vitis..............................................................................112 Adding and Associating an ELF File to an Embedded Design............................................114 UG994 (v2020.1) June 3, 2020 Send Feedback www.xilinx.com Designing IP Subsystems Using IP Integrator 3 Saving a Block Design with a New Name.............................................................................119 Comparing Two Block Designs..............................................................................................124 Packaging a Block Design...................................................................................................... 130 Chapter 5: Cross Probing Timing Paths..........................................................131 Chapter 6: Propagating Parameters in IP Integrator............................ 133 Using Bus Interfaces...............................................................................................................134 Parameter Propagation..........................................................................................................138 Parameters in the Customization GUI..................................................................................139 Parameter Mismatch Example.............................................................................................. 142 Chapter 7: Debugging IP Integrator Designs............................................. 143 Using the HDL Instantiation Flow in IP Integrator..............................................................144 Using the Netlist Insertion Flow............................................................................................ 159 Removing Debug Logic after Debug.................................................................................... 168 Chapter 8: Using Tcl Scripts to Create Projects and Block Designs 170 Exporting a Block Design to a Tcl Script in the IDE............................................................. 170 Saving Vivado Project Information in a Tcl File................................................................... 174 Chapter 9: Using IP Integrator in Non-Project Mode.............................177 Creating a Flow in Non-Project Mode...................................................................................177 Chapter 10: Updating Designs for a New Release....................................181 Upgrading a Block Design in Project Mode......................................................................... 181 Upgrading a Block Design in Non-Project Mode................................................................ 185 Selectively Upgrading IP in Block Designs........................................................................... 186 Chapter 11: Using the Platform Board Flow in IP Integrator............ 195 Selecting a Target Board........................................................................................................ 196 Downloading Third-Party Board Files from GitHub using the GUI...................................198 Creating a Block Design to use the Board Flow.................................................................. 200 Completing Connections in the Block Design..................................................................... 206 Archiving a Project when Board Flow is Used......................................................................208 Chapter 12: Using Third-Party Synthesis Tools in IP Integrator...... 209 Setting the Block Design as Out-of-Context Module..........................................................209 Creating an HDL or EDIF Netlist in Synplify......................................................................... 211 Creating a Post-Synthesis Project in Vivado........................................................................ 211 UG994 (v2020.1) June 3, 2020 Send Feedback www.xilinx.com Designing IP Subsystems Using IP Integrator 4 Adding Top-Level Constraints................................................................................................213 Adding an ELF File................................................................................................................... 214 Implementing the Design...................................................................................................... 215 Chapter 13: Referencing RTL Modules............................................................ 218 Referencing a Module.............................................................................................................218 XCI Inferencing........................................................................................................................ 224 IP and Reference Module Differences.................................................................................. 226 Inferring Generics/Parameters in an RTL Module..............................................................228 Inferring Control Signals in a RTL Module........................................................................... 229 Inferring AXI Interfaces.......................................................................................................... 234 Prioritizing Interfaces for Automatic Inference...................................................................237 HDL Parameters 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