HDMI Intel® Stratix 10 FPGA IP Design Example User Guide Updated for Intel® Quartus® Prime Design Suite: 21.1 IP Version: 19.6.0 Subscribe UG-20168 | 2021.05.12 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Stratix® 10 Devices...................................................................................................................... 4 1.1. Directory Structure................................................................................................ 4 1.2. Generating the Design............................................................................................8 1.3. Hardware and Software Requirements...................................................................... 9 1.4. Simulating the Design............................................................................................ 9 1.5. Compiling and Testing the Design...........................................................................10 1.6. Design Limitation.................................................................................................12 1.7. HDMI Intel FPGA IP Design Example Parameters...................................................... 12 2. HDMI 2.1 Design Example (Support FRL = 1)............................................................... 14 2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram................................................... 14 2.2. Creating RX-Only or TX-Only Designs..................................................................... 15 2.3. Hardware and Software Requirements.................................................................... 16 2.4. Directory Structure.............................................................................................. 17 2.5. Design Components............................................................................................. 21 2.5.1. HDMI TX Components...............................................................................21 2.5.2. HDMI RX Components.............................................................................. 24 2.5.3. Top-Level Common Blocks.........................................................................26 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering...................... 28 2.7. Design Software Flow........................................................................................... 31 2.8. Running the Design in Different FRL Rates...............................................................36 2.9. Clocking Scheme................................................................................................. 37 2.10. Interface Signals................................................................................................39 2.11. Design RTL Parameters ...................................................................................... 50 2.12. Hardware Setup.................................................................................................51 2.13. Simulation Testbench..........................................................................................52 2.14. Design Limitations..............................................................................................54 2.15. Debugging Features........................................................................................... 54 2.15.1. Software Debugging Message.................................................................. 55 2.15.2. SCDC Information from the Sink Connected to TX.......................................55 2.15.3. Clock Frequency Measurement ................................................................ 55 3. HDMI 2.0 Design Example.............................................................................................57 3.1. HDMI RX-TX Retransmit Design Block Diagram.........................................................57 3.2. Creating TX or RX Only Designs............................................................................. 58 3.3. Design Components............................................................................................. 59 3.4. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering...................... 64 3.5. Clocking Scheme................................................................................................. 67 3.6. Interface Signals..................................................................................................69 3.7. Design RTL Parameters ........................................................................................82 3.8. Hardware Setup ..................................................................................................83 3.9. Simulation Testbench........................................................................................... 84 3.10. Upgrading Your Design........................................................................................85 4. HDCP Over HDMI 2.0/2.1 Design Example.................................................................... 86 4.1. High-bandwidth Digital Content Protection (HDCP)................................................... 86 4.2. HDCP Over HDMI Design Example Architecture........................................................ 87 ® HDMI Intel Stratix 10 FPGA IP Design Example User Guide Send Feedback 2 Contents 4.3. Nios II Processor Software Flow............................................................................. 91 4.4. Design Walkthrough............................................................................................. 93 4.4.1. Set Up the Hardware................................................................................ 93 4.4.2. Generate the Design.................................................................................94 4.4.3. Include HDCP Production Keys................................................................... 94 4.4.4. Compile the Design................................................................................ 102 4.4.5. View the Results.................................................................................... 102 4.5. Protection of Encryption Key Embedded in FPGA Design.......................................... 104 4.6. Security Considerations.......................................................................................105 4.7. Debug Guidelines............................................................................................... 105 4.7.1. HDCP Status Signals...............................................................................106 4.7.2. Modifying HDCP Software Parameters....................................................... 106 4.7.3. HDCP Key Mapping from DCP Key Files......................................................107 4.7.4. Frequently Asked Questions (FAQ)............................................................113 5. HDMI Intel Stratix 10 FPGA IP Design Example User Guide Archives.......................... 115 6. Document Revision History for the HDMI Intel Stratix 10 FPGA IP Design Example User Guide............................................................................................................. 116 ® Send Feedback HDMI Intel Stratix 10 FPGA IP Design Example User Guide 3 UG-20168 | 2021.05.12 Send Feedback 1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Stratix® 10 Devices The HDMI Intel® FPGA IP design example for Intel Stratix® 10 devices features a simulating testbench and a hardware design that supports compilation and hardware testing. The HDMI Intel FPGA IP offers the following design examples: • HDMI 2.1 RX-TX retransmit design with fixed rate link (FRL) mode enabled • HDMI 2.0 RX-TX retransmit design • HDCP over HDMI 2.0 design Note: The HDCP feature is not included in the Intel Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https:// www.intel.com/content/www/us/en/broadcast/products/programmable/ applications/connectivity-solutions.html. When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. Figure 1. Development Steps Compilation Functional (Simulator) Simulation Design Example Compilation Hardware Generation (Quartus Prime) Testing Related Information • HDMI Intel FPGA IP Release Notes Describes changes to the IP in a particular release. • HDMI Intel FPGA IP User Guide 1.1. Directory Structure The directories contain the generated files for the HDMI Intel FPGA IP design example. Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, eASIC, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015 at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. 1. HDMI Intel® FPGA IP Design