41.3 Fault Models for Embedded-DRAM Macros Mango C.-T. Chao, Hao-Yu Yang, Rei-Fu Huang†, Shih-Chin Lin‡, Ching-Yu Chin Dept. of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan †MediaTek Inc., Hsinchu, Taiwan ‡ United Microelectronics Corporation, Hsinchu, Taiwan {[email protected], [email protected], [email protected], [email protected], [email protected]} Abstract DRAM cell can meet its specification. In the functional testing, we test whether the DRAM-cell array and its peripheral cir- In this paper, we compare embedded-DRAM (eDRAM) test- cuits can function correctly at different operating modes, which ing to both SRAM testing and commodity-DRAM testing, since combine different cycle latencies with different clock frequen- an eDRAM macro uses DRAM cells with an SRAM interface. cies for special applications, such as the burst mode and page We first start from an standard SRAM test algorithm and dis- read/write. To cover various fault models for the DRAM array, cuss the faults which are not covered in the SRAM testing but several test algorithms, such as checkerboard, address comple- should be considered in the DRAM testing. Then we study the ment, March, row/column disturb, self-refresh, XMOVI, and behavior of those faults and the tests which can detect them. butterfly, need to be applied. Applying all the above algo- Also, we discuss how likely each modeled fault may occur on rithms at different operating modes is time-consuming, and eDRAMs and commodity DRAMs, respectively. hence, in reality, most DRAM companies price their DRAM chips differently according to the length of the applied test. Categories and Subject Descriptors With this price model, DRAM companies need to analyze their B.8.1 [Hardware]: Reliability, Testing, and Fault-Tolerance process as well as their memory design to rank the fault models by their possibility of occurrence. Then, the test engineers can choose a proper combination of test algorithms to cover the General Terms high-ranked faults as much as possible when the length of the Design applied test is limited. Testing eDRAMs is quite different from testing commod- Keywords ity DRAMs due to the following reasons. First of all, most eDRAM macros use the SRAM interface (the so-called 1T- Memory testing, embedded DRAM SRAM architecture), which consists of no address multiplexer (no CAS, RAS) and can auto-refresh. Second, unlike com- 1. INTRODUCTION modity DRAM, whose application might be unknown before With the continually growing need to an effective and eco- the fabrication, eDRAM macros are more application-specific nomic embedded-memory core in the SoC era, researchers at- and hence have only one operating mode, meaning that one cy- tempt to carry DRAM’s advantages, such as high density, struc- cle latency at only one operating frequency needs to be tested. ture simplicity, low-power consumption, and low cost [1], from Due to the simplicity of eDRAM’s interface, testing eDRAMs a commodity memory into a SoC. In the past decade, a lot is more like testing SRAMs and requires a shorter test al- research effort has been put into the area of the embedded- gorithm than testing commodity DRAMs. However, testing DRAM (eDRAM) technologies, such as deep-trench capacitor eDRAM is not as simple as testing SRAMs since some fault with bottle etch [2], planar capacitor [3] [4], shallow trench ca- models which may not be considered in SRAM testing, such pacitor [4], and metal-insulator-metal (MIM) capacitor [3] [5], as retention faults and coupling faults, should be considered to reduce eDRAM’s process adders to the CMOS process. How- in eDRAM. Third, the process of eDRAMs is different from ever, few previous research works have discussed the testing that of commodity DRAMs, meaning that their storage capac- strategies used for eDRAMs, which cannot be directly carried itors, bit lines, word lines, transistors models, number of metal from the testing of commodity DRAMs. layers, and wire models are all different. As a result, the possi- The conventional DRAM testing contains two main tasks: bility of a fault’s occurrence for eDRAMs is different from that the retention testing and the functional testing. In the reten- for commodity DRAMs as well. tion testing, we test whether the data retention time of each In addition, when a bare DRAM die is integrated to a system- in-package, the responsibility of testing the DRAMs is on the DRAM provider. However, when an eDRAM macro is inte- Permission to make digital or hard copies of part or all of this work for grated to a system-on-chip (SoC), the responsibility of testing personal or classroom use is granted without fee provided that copies are the eDRAMs is transferred to the system integrator. Testing not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, eDRAM macros in an SoC chip relies on the BIST circuitry to republish, to post on servers or to redistribute to lists, requires prior to enhance the test accessibility of the SoC testing [6][7][8]. specific permission and/or a fee. Its test application time depends on the efficiency of the test DAC’09, July 26-31, 2009, San Francisco, California, USA scheduling among various types of embedded cores. On the Copyright 2009 ACM 978-1-60558-497-3/09/07....10.00 other hand, testing commodity DRAMs (especially the MCM 714 DRAM KGDs) seldom uses BIST in practice and relies more Bank 0 (64x64x16) Bank 0 (64x64x16) on the the parallel testing capability provided by the memory Bank 1 (64x64x16) Bank 1 (64x64x16) testers to shorten the average test time. Several BIST schemes are proposed for the embedded DRAM testing [9][10][11][12]. However, these previous works mainly focus on the architec- . ture and the automatic generation of the BIST circuitry, not 8Mb 8Mb eDRAM eDRAM on the testing algorithms and methodologies. Array Array . Driver WL Driver WL . In this paper, we would like to share our experience in test- . ing an UMC 65nm eDRAM macro. We first introduce the (Address Decoder) overall architecture of the eDRAM macro under test and the Local Control Circuitry Bank 126 (64x64x16) Bank 126 (64x64x16) differences between commodity-DRAMs testing and eDRAMs Bank 127 (()64x64x16) Bank 127 (()64x64x16) testing. Since an eDRAM macro uses an SRAM interface, we start from a standard SRAM algorithm and then discuss the Read/Write Path Main Control Read/Write Path fault models which are not covered by the SRAM algorithm but (Global S.A.) Circuitry (Global S.A.) should be particularly considered when testing DRAMs. Next, Data Out Data In we discuss the impact of those faults on both eDRAMs and Data In Data Out Control [0:15] [0:15] Signal [16:31] [16:31] commodity DRAMs, and suggest a test sequence to cover each of those faults. Also, we discuss how likely each modeled fault pass/fail may occur on eDRAMs and commodity DRAMs, respectively. BIST 2. BACKGROUND Figure 1: Architecture of a UMC 16Mb eDRAM macro. 2.1 Overview of an Embedded-DRAM Macro G1 RC1JV 1Q`RRC1JV Figure 1 shows the block diagram of a 16Mb eDRAM macro : V `VJH.H:]8 `:] used in our SoC design. This eDRAM macro utilizes deep 1 trench capacitors and is implemented in a UMC 65nm low- JU Q%`HV JU R`:1J leakage logic process. Figure 2 shows a cross-section view of an eDRAM cell in our design. The word size on the interface of ]R1VCC this eDRAM macro is 32 bits. Due to the use of ECC, we need to add 6-bit more memory cells to the physical array for each word, and hence the physical data stored in the memory array Figure 2: Illustration of an eDRAM cell. is 38 bits per word. The size of the eDRAM macro is around 4mm2, which contains two symmetric eDRAM arrays. Each array contains 128 banks, and each bank contains 64 word-lines bit-line twist for a column reverses the physical-value/logical- anditsownlocalsenseamplifier. Each word-line on each array value relation of the cells below that twist. is connected to 64 half-words, and the data-width of each half- During the eDRAM testing, the data background written word is 19 bits. Note that the layout topology of the eDRAM into or read from the memory macro should represent cell’s array utilizes the distributed folding scheme, where the ith bit physical value instead of its logical value. Therefore, when of the jth word is adjacent to the ith bit of the (j+1)th word, designing the BIST circuitry, we need to build a scramble ta- not the (i+1)th bit of the original jth word. A physical 38- ble to map the physical value described in the test algorithm bit word is read out from or written into the memory array to its corresponding logical value for a given address [13][14]. through the ECC circuitry, which encodes a 32-bit word into a Those logical values then form the functional test patterns or 38-bit word or decodes a 38-bit word to a 32-bit word. When expected responses during testing. This scramble table can be operating at 100 MHz, the bandwidth of this eDRAM macro implemented by a simple two-level logic, whose inputs contain is 3.125 Gb/s (32 bits x 100 MHz). few least significant bits and most significant bits of an address. In modern memory designs, scrambling techniques are com- In addition, when performing March algorithm, the sequence monly used to optimize memory’s layout geometry, address of the activated word-lines also needs to follow the physical se- decoder, cell area, performance, yield, and I/O pin compatibil- quence, not logical address sequence.