Capacitance-Voltage Measurements: an Expert System Approach Thesis submitted by James Austin Walls for the degree of Doctor of Philosophy Edinburgh Microfabrication Facility Department of Electrical Engineering University of Edinburgh United Kingdom Abstract The problems for automating capacitance-voltage (C-V) based process monitoring tests are many and varied. The challenges are: interpreting numerical and graphical data, and secondly, performing tests in a correct sequence whilst applying the appropriate simplifying assumptions in the data analysis. A progressive series of experiments using connectionism, pattern-recognition and knowledge-based techniques were researched, culminating with the development of a fully automatic hybrid system for the control of the Hewlett-Packard HP4061 semiconductor test system. This thesis also includes a substantial review of, and guide to, the theory and practice of the high-frequency, low-frequency and pulsed C-V measurements, conductance-voltage and capacitance-time measurements. Several novel software packages have been written (CV-ASSIST, CV- EXPLORE), including a rule-based expert system (CV-EXPERT) for the control and opportunistic sequencing of measurements and analyses. The research concludes that the new approaches offer the full power and sensitivity of C-V measurements to the operator without the burden of careful procedure, interpretation of the data, and validation of the algorithms used. Acknowledgements This thesis is the result of a Cooperative Award in Science and Engineering (CASE) with Hewlett Packard (UK) Ltd.. The support from the U.K. Science and Engineering Research Council (grant No. GR/F 30499) is also gratefully acknowledged. I would like to express my thanks to my supervisor, Dr. A.J. Walton, for his enthusiastic help, encouragement, and guidance during the course of this research. My thanks also go to my industrial supervisor, Dr. T.M. Crawford of Hewlett Packard Ltd. at South Queensferry for providing the necessary internal liason and support for this project. I would also like to extend my gratitude to the many employees of Hewlett Packard Ltd., particularly David Newton, Stewart Wilson and Graeme Gourly, who provided helpful advice regarding hardware and software for this project. My greatest thanks are due to the staff of the Edinburgh Microfabrication Facility, in particular Prof. J.M. Robertson, Mr. A.M. Gundlach and Dr. R. Holwill for their guidance and support, and to the many technicians, past and present, who have helped in the production of test wafers. Additionally, I have benefitted considerably from many discussions with other members of the Electrical Engineering Department, particularly Dr. C.F.N. Cowan and Dr. A.R. Mirzai. Furthermore, this project could not have progressed without the influence of the Artificial Intelligence Applications Institute. My particular, thanks, therefore, go to Bert Hutchings, Robert Rae, Paul Chung, and Peter Ross for their assistance with, and interest in my research. It goes without saying that this research would not have been so interesting were it not for the inspiration, encouragement and advice I gained from my fellow research students. Finally, my thanks go to Jane Glachan for diligently typing the draft, and for her infinite patience and moral support. Declaration I declare that the research documented in this thesis is original and entirely of my own making, except where indicated to the contrary. James Austin Walls Contents Chapter 1: Introduction . 1 Chapter 2: Silicon Processing & Process Control .................. 5 2.1. IC Manufacturing ................................................................. 5 2.2. Review of the MOS Process .................................................... 7 2.2.1. Cleaning & Surface Preparation .......................................... 7 2.2.2. Oxidation ...................................................................... 9 2.2.3. Doping ........................................................................ 10 2.2.4. Interconnect Material Deposition ....................................... 10 2.2.5. Lithography .................................................................. 11 2.2.6. Etching ....................................................................... 11 2.2.7. Annealing .................................................................... 12 2.2.7.1. Implant Activation Anneal .......................................... 12 2.2.7.2. Post-Oxidation Anneal ................................................ 13 2.2.7.3. Post-Metallisation Anneal ............................................ 13 2.3. C-V Testing For Process Monitoring and Control ........................ 13 2.3.1. Process Control Parameters .............................................. 14 2.4. VLSI Specifications ............................................................. 15 2.4.1. Specifications For An Oxide .............................................. 16 2.4.2. Specifications For The Substrate ........................................ 17 2.4.3. General Considerations For VLSI Processing ........................ 20 2.5. Process Automation ............................................................. 21 Chapter 3: The MOS Capacitor ...........................................24 3.1. Introduction .......................................................................24 3.2. Structure and Terminology ....................................................25 3.2.1. Charges in The MOS System ............................................27 3.3. Bias Regimes of The MOS Capacitor .......................................29 3.4. Energy Band Diagrams .........................................................31 -I - 3.5. Measuring Equipment . 36 3.5.1. Probe Station Hardware ...................................................36 3.5.2. Capacitance Meter .........................................................38 3.6. Sample Preparation .............................................................39 3.6.1. Contacting the MOS Capacitor ..........................................40 3.6.2. Edge Effects .................................................................41 3.6.3. Sample Fabrication .........................................................43 3.7. Conclusions .......................................................................43 Chapter 4: The Capacitance-Voltage Technique ..................46 4.1. Introduction ......................................................................46 4.2.. Non-Ideal MOS Behaviour ....................................................46 4.3. Equilibrium C-V Measurements .............................................47 4.3.1. Modelling the High-Frequency C-V Relation ........................ 47 4.3.1.1. Non-Uniform Doping ................................................. 51 4.3.2. Parameter Extraction ...................................................... 52 4.3.2.1. Substrate Type ......................................................... 52 4.3.2.2. Oxide Thickness/Capacitance ....................................... 52 4.3.2.3. Substrate Doping ...................................................... 54 4.3.2.4. Flatband Voltage ...................................................... 56 4.3.3. Oxide Charges ............................................................... 58 4.3.3.1. Fixed Charge ........................................................... 59 4.3.3.2. Mobile Charge ......................................................... 60 4.3.3.3. Oxide Trapped Charge Q0................................................. 63 4.3.3.4. Interface Trapped Charge Q., ,D ........................................ 64 4.4. Typical Non-Standard Curves ................................................. 69 Series Resistance .............................................................. 69 Oxide Resistance .............................................................. 70 Poor MOS Contacts .......................................................... 72 Interface Trapped Charge ...................................................73 Localised Charge Non-Uniformities .......................................73 Capacitive Substrate Top Contacts ........................................75 Effect of Incident Light and Elevated Temperatures ..................76 Enhancement/Threshold-Adjust Implants ................................77 Depletion/Compensating Implants . 78 Short Minority Carrier Generation Lifetime ............................ 80 Lateral Inversion Layer Spreading ........................................ 82 4.5. Pulsed C-V Dopant Profiling .................................................. 83 4.5.1. Limited Depth .............................................................. 85 4.5.2. Limited Resolution ......................................................... 85 4.5.3. Interface Proximity Limitation .......................................... 86 4.5.4. Interface Trap Distortion ................................................. 88 4.5.5. Differential Noise ........................................................... 90 4.6. Conductance-Voltage Measurements ........................................ 93 4.7. Quasi-Static C-V Measurements .............................................. 97 4.8. Capacitance-Time Measurements ........................................... 100 4.9. Conclusion ........................................................................ 105 Chapter 5: Connectionist Learning Systems ....................... 113 5.1. Introduction .....................................................................113