See all versions of this document Vivado Design Suite User Guide: Logic Simulation UG900 (v2020.1) June 3, 2020 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 06/03/2020 Version 2020.1 Chapter 3: Simulating with Third-Party Simulators Added table 8 and table 9 General Updates Updated Using Simulation Settings in chapter 2 General Updates Updated Object Windows in chapter 4 UG900 (v2020.1) June 3, 2020Send Feedback www.xilinx.com Vivado Design Suite User Guide: Logic Simulation 2 Table of Contents Revision History...............................................................................................................2 Chapter 1: Logic Simulation Overview............................................................... 7 Supported Simulators.................................................................................................................7 Simulation Flow .......................................................................................................................... 8 Language and Encryption Support ........................................................................................ 11 Chapter 2: Preparing for Simulation..................................................................12 Using Test Benches and Stimulus Files.................................................................................. 12 Pointing to the Simulator Install Location............................................................................. 13 Compiling Simulation Libraries............................................................................................... 14 Using Xilinx Simulation Libraries.............................................................................................19 Using Simulation Settings........................................................................................................ 28 Adding or Creating Simulation Source Files.......................................................................... 32 Generating a Netlist..................................................................................................................34 Chapter 3: Simulating with Third-Party Simulators................................. 37 Running Simulation Using Third Party Simulators with Vivado IDE................................... 39 Dumping SAIF for Power Analysis...........................................................................................42 Dumping VCD............................................................................................................................ 44 Simulating IP..............................................................................................................................45 Using a Custom DO File During an Integrated Simulation Run.......................................... 45 Running Third-Party Simulators in Batch Mode....................................................................48 Chapter 4: Simulating with Vivado Simulator..............................................49 Running the Vivado Simulator.................................................................................................49 Running Functional and Timing Simulation...........................................................................67 Saving Simulation Results........................................................................................................ 69 Distinguishing Between Multiple Simulation Runs...............................................................70 Closing a Simulation................................................................................................................. 70 Adding a Simulation Start-up Script File.................................................................................71 Viewing Simulation Messages................................................................................................. 72 Using the launch_simulation Command................................................................................ 73 UG900 (v2020.1) June 3, 2020Send Feedback www.xilinx.com Vivado Design Suite User Guide: Logic Simulation 3 Re-running the Simulation After Design Changes (relaunch).............................................74 Using the Saved Simulator User Interface Settings..............................................................75 Chapter 5: Analyzing Simulation Waveforms with Vivado Simulator...................................................................................................................... 77 Using Wave Configurations and Windows.............................................................................77 Opening a Previously Saved Simulation Run.........................................................................78 Understanding HDL Objects in Waveform Configurations .................................................79 Customizing the Waveform..................................................................................................... 82 Controlling the Waveform Display ......................................................................................... 88 Organizing Waveforms.............................................................................................................92 Analyzing Waveforms............................................................................................................... 94 Analyzing AXI Interface Transactions..................................................................................... 99 Chapter 6: Debugging a Design with Vivado Simulator....................... 114 Debugging at the Source Level............................................................................................. 114 Forcing Objects to Specific Values.........................................................................................118 Power Analysis Using Vivado Simulator............................................................................... 126 Using the report_drivers Tcl Command................................................................................128 Using the Value Change Dump Feature...............................................................................128 Using the log_wave Tcl Command........................................................................................ 129 Cross Probing Signals in the Object, Wave, and Text Editor Windows.............................131 Chapter 7: Simulating in Batch or Scripted Mode in Vivado Simulator.....................................................................................................................137 Exporting Simulation Files and Scripts................................................................................. 137 Running the Vivado Simulator in Batch Mode.....................................................................143 Elaborating and Generating a Design Snapshot, xelab......................................................145 Simulating the Design Snapshot, xsim.................................................................................156 Example of Running Vivado Simulator in Standalone Mode............................................. 159 Project File (.prj) Syntax..........................................................................................................160 Predefined Macros.................................................................................................................. 161 Library Mapping File (xsim.ini).............................................................................................. 161 Running Simulation Modes....................................................................................................162 Using Tcl Commands and Scripts .........................................................................................165 export_simulation ...................................................................................................................166 export_ip_user_files.................................................................................................................169 UG900 (v2020.1) June 3, 2020Send Feedback www.xilinx.com Vivado Design Suite User Guide: Logic Simulation 4 Appendix A: Compilation, Elaboration, Simulation, Netlist, and Advanced Options..................................................................................................171 Compilation Options...............................................................................................................171 Elaboration Options................................................................................................................ 174 Simulation Options................................................................................................................. 175 Netlist Options.........................................................................................................................178 Advanced Simulation Options............................................................................................... 178 Appendix B: SystemVerilog Support in Vivado Simulator................... 180 Targeting SystemVerilog for a Specific File..........................................................................180 Testbench Feature...................................................................................................................187 Appendix C: Universal Verification Methodology Support................. 196 Appendix D: VHDL