(1) Application Report SLUA770A–March 2016–Revised May 2018 UCC27531 35-V Gate Driver for SiC MOSFET Applications Richard Herring........................................................................................... High Power Driver Solutions ABSTRACT SiC MOSFETs are gaining popularity in many high-power applications due to their significant switching performance advantages. SiC MOSFETs are also available with attractive voltage ratings and current capabilities. However, the characteristics of SiC MOSFETs require consideration of the gate-driver circuit to optimize the switching performance of the SiC device. Although SiC MOSFETs are not difficult to drive properly, many typical MOSFET drivers may result in compromised switching speed performance. The UCC27531 gate driver includes features and has operating parameters that allow for driving SiC power MOSFETs within the recommended optimum drive configuration. This application note reviews the characteristics of SiC MOSFETs and how to drive them to achieve the performance improvement that SiC can bring at the system level. The features of UCC27531 to achieve optimal performance of SiC are explained and results from a demonstration circuit are provided. 1 Introduction In the past, the majority of applications such as uninterruptible power supplies (UPS), photovoltaic (PV) inverters, and motor drive have utilized IGBTs for the power devices due to the combination of high- voltage ratings exceeding 1 kV and high current capability. Usable switching frequency of IGBTs has typically been limited to 20–30 kHz, due to the high turnoff losses caused by the long turnoff current tail. Design comparisons have shown that SiC MOSFET designs can operate at considerably higher switching frequency and achieve the same or better efficiency. Although the device cost of the SiC MOSFETs are higher than the equivalent IGBTs, the significant savings in transformer, capacitor, and enclosure size results in a lower system cost. The availability of Silicon MOSFETs with voltage ratings up to 900 V and low RDS(on) below 150 mΩ is improving. Beyond 900 V, low RDS(on) MOSFETs are not available. Although Si-MOSFET designs can be realized at considerably higher switching frequency than IGBTs, the cost of high-current and high-voltage Si MOSFETs is considerably higher than IGBTs. 2 Advantages of Wide Bandgap SiC The primary advantage of SiC MOSFETs over Si MOSFETs is the availability of very low RDS(on) and high voltage ratings; up to 1200 V at 25 mΩ. SiC devices are capable of faster switching speeds than Si MOSFETs due to the very low parasitic capacitance and associated charge during switching, refer to Table 1 for details. Although the SiC MOSFET is driven with higher peak-to-peak gate-to-source voltage, per the device recommendation, the total gate charge of the SiC device is over 15 times lower than an equivalent Si MOSFET. A characteristic that must be considered in any converter design is the RDS(on) at the anticipated highest junction temperature. SiC MOSFETs exhibit a much lower increase in RDS(on) at high temperature than Si MOSFETs. The example SiC MOSFET curves indicate approximately 1.25 times increase in RDS(on) from 25°C to 125°C, where the Si MOSFET curves indicate approximately 2.2 times increase in RDS(on). At 125°C the conduction losses are higher on the Si MOSFET since the RDS(on) is approximately 265 mΩ versus the SiC RDS(on) of 150 mΩ. (1) All trademarks are the property of their respective owners. SLUA770A–March 2016–Revised May 2018 UCC27531 35-V Gate Driver for SiC MOSFET Applications 1 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated SiC MOSFET Characteristics www.ti.com Table 1. SiC vs Si MOSFET Parameter Table 900 V, 120 mΩ 900 V/120 mΩ Qg (nC) td(on) (ns) trise (ns) td(off) (ns) Tfall (ns) RDS(on) factor 25–125°C Si N-Ch 270 70 20 400 25 2.2 SiC N-Ch 17.3 27 10 25 8 1.25 Si IGBT characteristics include high voltage ratings and low saturation voltage at very high current, resulting in the equivalent of a very low RDS(on) MOSFET. The well-known switching frequency limitation of IGBTs is the long current tail during turnoff which can exceed 300 ns even with the higher switching frequency rated devices. The IGBT long collector current fall time results in turnoff switching losses that can be 6 to 10 times higher than SiC MOSFETs. 3 SiC MOSFET Characteristics SiC MOSFETs have a relatively low transconductance compared to Si MOSFETs. The result is a higher gate-to-source voltage required to achieve the lowest VDS saturation voltage at high drain current. Where most Si MOSFETs achieve low VDS saturation at 8 V to 10 V on the gate to source, SiC MOSFETs typically require 15 V to 20 V VGS to achieve low VDS saturation. The turnon threshold voltage of SiC is similar or lower than Si MOSFETs which results in a larger VGS transition when the SiC MOSFET is operating as a variable resistance. The fast switching speed and low turnon threshold of SiC MOSFETs requires a negative VGS level during turnoff. Depending on the device, –2 V to –5 V drive is recommended for SiC devices. Although the MOSFET parasitic CDS (CRSS) is very low, the high VDS dV/dt during turnoff can result in coupling enough charge from the drain-to-gate capacitance to reach the threshold voltage if negative drive and a close- coupled driver layout is not in place. 3.1 MOSFET Switching Transient Process and Effects of MOSFET Parasitics The details of the MOSFET turnon and turnoff transient events are similar for Si and SiC MOSFETs. Both devices have parasitic CDS, CGD, and CGS. Also Si and SiC CGD and CDS are dynamic, depending on the voltage level, much higher capacitance at a lower voltage level, and CGS is relatively flat. There are detailed studies of the MOSFET switching transients from universities and device manufacturers. The following is a general summary of the switching transients in a continuous current power train for reference. 3.1.1 MOSFET Turnon Transient The turnon event is generally the process of charging the MOSFET parasitic capacitances to the voltage level required to achieve low RDS(on). A basic step-by-step process is presented. Refer to Figure 1 and Figure 2 for the current flow and timing illustrations: 1. Pulse-width modulation (PWM) and driver start charging CGS to the MOSFET turnon plateau. • The MOSFET plateau is defined as the VGS threshold plus the voltage delta required to conduct the current amplitude flowing in the inductor, IL. The transconductance of the MOSFET and current level determine the additional voltage required over the threshold voltage. 2. At the VGS plateau, the VDS begins to fall to ground. During the fall time to ground, the negative dV/dt of the drain generates a current flowing through CGD that opposes the current from the gate-driver circuit, known generally as Miller effect current. The duration of this current flow is the VDS fall time. Also note that the internal FET gate terminal is a lower voltage potential than observed on the gate terminal, due to the Miller current flowing into the internal FET resistance, RG. 3. After the VDS fall time, the gate is charged to the level determined by the driver source voltage. The MOSFET achieves the lowest RDS(on) based on the particular device parameters. Typically 8–10 V for high voltage Si MOSFETs and 15–20 V for SiC MOSFETs. 2 UCC27531 35-V Gate Driver for SiC MOSFET Applications SLUA770A–March 2016–Revised May 2018 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated www.ti.com SiC MOSFET Characteristics IL PWM time V + IN - VOUT VDS ID ID CGD VDS Falling VDD VDD OUTH RON 6 VDS VGS CDS OUTL ROFF EN + RG PWM 5 VPlateau CGS IG IN GND 4 Vth IG VGS Rising t0 t1 t2 t3 t4 Figure 1. Turnon Circuit with Parasitic Capacitance Figure 2. Turnon Waveform 3.1.2 MOSFET Turnoff Transient The turnoff event is generally the process of discharging the MOSFET parasitic capacitances to the voltage level required to achieve the off state. A basic step-by-step process is presented in the following list. Refer to Figure 3 and Figure 4 for the current flow and timing illustration. 1. PWM and driver start discharging CGS to the MOSFET turnoff plateau. 2. At the VGS plateau, the VDS begins to rise from ground. During the rise time of VDS, the positive dV/dt of the drain generates a current flowing through CGD that opposes the current from the gate-driver circuit, known generally as Miller-effect current. The duration of this current flow is the VDS rise time. Also note that the internal FET-gate terminal is at a higher voltage than observed on the gate terminal due to the Miller current flowing through the internal FET resistance, RG. 3. After the VDS rise time, the gate is discharged from the plateau voltage to the driver ground reference. IL + VIN PWM í VOUT time ID VDS Rising CGD v VDD OUTH DS RON VDD 6 iD CDS OUTL ROFF EN RG PWM + 5 VCC CGS IG v IN GND GS 4 VGS Falling iG Vth Figure 3. Turnoff Circuit with Parasitic Capacitance Figure 4. Turnoff Waveform SLUA770A–March 2016–Revised May 2018 UCC27531 35-V Gate Driver for SiC MOSFET Applications 3 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated UCC27531 Advantages for SiC MOSFET Applications www.ti.com 4 UCC27531 Advantages for SiC MOSFET Applications The driver circuit voltage required for driving SiC MOSFETs within the recommended conditions includes the sum of the positive gate-drive level and negative-drive level.