MEMORIES Memory Outline • Overview • Array Memory View 4: memories for ASICs – Array Memory View 1 and FPGAs – Array Memory View 2: Types – On-chip macros • Read/Write • ASICs • ROM • FPGAs • NVRWM – On-chip standard cell – Array Memory View 3 • ASICs • Combinational • FPGAs • Technically sequential – Off-chip • Sequential • Synthesized standard cell memories • 6T SRAM cell – Verilog • SRAM circuits and layout – Timing • Multi-port SRAM – ROM: standard cell verilog • DRAM – ROM: FPGA block RAM • ROM circuits and layout © B. Baas 238 Array Memory View 1: A Component of Digital Systems • Three primary components of digital systems – Datapath (does the work) – Control (manager) – Memory (storage) • “Single bit” (“foreground”) – Clockless latches e.g., SR latch – Clocked transparent latches e.g., D latch – Clocked edge-triggered flip flops e.g., D FF • “Array” memories (“background”) © B. Baas 239 Memories • Use in general digital processors – Instructions – Data • Usage is more widespread in DSP, multimedia, embedded processors – Buffering input/intermediate/output data (e.g., rate matching) – Storing fixed numbers (e.g., coefficients) – Often relatively small (e.g., 8-64-256 words) and numerous (dozens are not unusual) • Key design goal: density, especially for the memory cells. This means fitting the largest amount of © B. Baasmemory storage into a certain amount of chip area 240 Array Memory View 2: Types of Memories 1. Read-write memories – SRAM: Static random access memory • Data is stored as the state of a bistable circuit typically using “back-to-back” inverters • State is retained without refresh as long as power is supplied – DRAM: Dynamic random access memory • Data is stored as a charge on a capacitor • State leaks away, refresh is required 2. ROM: Read-only memory, non-volatile – Basic ROM – mask programmed at design time – PROM: Programmable read-only memory; typically programmed at manufacture time by a “PROM burner” • Using fuse or anti-fuse circuits – Synthesized from standard cells 3. NVRWM: Non-volatile read-write memory – EPROM: Erasable ROM, erasable with UV light © B. Baas 241 – Flash: ROM at low voltages, writable at high voltages Memory View 3: Memory Logical Categories • Combinational (output depends on present inputs only) – ROM: read-only memory – May be straight-through truly-combinational, or registered • Feels like Combinational but technically Sequential – PROM: programmable read-only memory – EPROM: ROM, but erasable with UV light • Sequential (output depends on present and past inputs) – SRAM: static memory – DRAM: dynamic memory – Flash: ROM at low voltages, writable at high voltages © B. Baas 242 Basic Memory Inputs and Outputs • The basic memory structure includes a write port and a read port as shown in the figure – Clocked or Synchronous memories include a clock input – A read-enable input (rd_en) is not needed for functionality but is often included to enable reduced power dissipation when read operations are not needed clock wr_addr write port wr_data wr_en Memory rd_addr rd_data rd_en © B. Baas read port 243 Memories • Memories generally contain several components: bitlines – Array of cells – Address decoder … … … – Write circuitry – Read circuitry … (sense amplifiers) word cell cell cell – wordlines or – bitlines address cell cell cell … • Interface signals decoder wordlines – Address (one for each port) cell cell cell … – Data (one for each port) – Enable_write – Enable_read (likely) write/read – Clock (sometimes) Addr circuitry © B. Baas 244 Data_rd Data_wr Memories—Differential bitlines • Differential bitlines (bitline and bitline_) bitlines … … require more area … wordline but dramatically increase robustness cell cell cell … and speed Address – Much smaller decoder cell cell cell … voltage differences can be detected cell cell cell … – Much more noise can be tolerated Read / (Write) circuitry © B. Baas 245 Six-Transistor (6T) SRAM Cell BL BL Q Q WL • Cross-coupled inverters: a bistable element (two stable states) • Density is critically important in memories – Single NMOS used for reading/writing – A lot of effort spent packing transistors and even pushing process design rules just for the 6T memory cell—the area of a 6T cell is typically one of the top critical parameters of a fabrication technology! © B. Baas 246 116 SRAM Cell • Cross-coupled inverters: a bistable element (two stable states) • Density is critically important in memories – Single NMOS used for reading/writing – A lot of effort spent packing transistors and even pushing process design rules just for the 6T memory cell © B. Baas 247 Retrieved November 17, 2016 Layout: 6-Transistor (6T) Cell Bitline Bitline_ • Two 6T SRAM cells • Wordlines horizontal • Bitlines vertical • Vdd and Gnd horizontal Wordline0 Wordline1 Gnd © B. Baas Vdd 248 6-Transistor (6T) Cells • Micro-photographs of fabricated Vdd 6T SRAM memory cells • The devices are partially built with diffusion and polysilicon only—metal interconnect is shown where it might be located Gnd Gnd Vdd Wordline Wordline Wordline Vdd Gnd Bitline Bitline_ Intel 65 nm 0.57 μm2 6T cell © B. Baas 249 [http://www.electroiq.com/articles/sst/print/volume-47/issue-2/departments/tech-news/technology-news.html] 6-Transistor (6T) Cells • Micro-photograph of 0.16 µm2 6T SRAM cells from an AMD Radeon graphics processor fabraicated in TSMC’s 28 nm HP process © B. Baas 250 [Chipworks] Layout: 6T cell array Cell array Sense amplifiers and write circuits © B. Baas 251 Layout: Memory Array • 128 words x 36 bits • Single-ported 6T SRAM • Low-power hierarchical bitline structure Wordline decoders Sense amplifiers © B. Baas 252 Layout: Memory array • Layout issues cell – Cell density is critical array – Decoder design should probably not use full N-word fanout • Predecoding address bits Wordline decoders reduces loading of critical decoder signals – Routing of Vdd and Gnd to supply adequate current requires planning Sense amplifiers © B. Baas 253 Memory Array • Human hair on a 256 Kbit memory chip 254 © B. Baas Source: Helmut Föll Multi-ported SRAM • Frequently used in register files – Classic RISC computers have 1 write and 2 read ports – Modern multiple-instruction-issue computers can have many ports (22 (12 Rd, 10 Wr) in Itanium [ISSCC 05]) • More commonly use single-ended (non-differential) bitlines Addr/Data Addr/Data 2 write ports Memory 4 read ports © B. Baas 259 Multi-ported SRAM • Example: one write port, two read ports Read bitline 0 Read bitline 1 Write bitline Write wordline Read wordline 0 Read wordline 1 © B. Baas 260 116 Multi-ported SRAM • Example: one write port, two read ports • If the feedback inverter is not tri-statable during writes, it must be made weak to permit writes, especially during a high value (Vdd) on the bitline Read bitline 0 Read bitline 1 Write bitline Write wordline Read wordline 0 Read wordline 1 © B. Baas 261 Layout: Dual-ported memory cell • 10T one-read, write bitline Vdd Gnd read bitline one-write port read wordline_ • Operates at very write wordline_ low supply voltages Vdd Gnd write wordline read wordline © B. Baas 262 Layout: Dual-ported memory cell array • Eight 10T dual- ported memory cells © B. Baas 263 Layout: Dual-ported memory array • 10T one-read, one-write port • 16 words x 40 bits read write decoder decoder bitline drivers and © B. Baas sense amplifiers 264 DRAM • Smaller cell size (1T cell) BL – One transistor to access cell Q – Often has special structure for cell capacitor (trench capacitor) that is not available in standard fabrication WL technologies • Single bitline to read and write the memory cell • Must be periodically refreshed • Write operation: – Wordline at Vdd – Bitline value stored on cell capacitor “Trench” capacitor © B. Baas 265 DRAM • Classic DRAM – High density dedicated DRAM chips typically packaged in DIMMs – Top manufacturers include: Samsung (47%), Hynix (26%), Micron (19%), and others. [Source: Statista, for Q2 2016] • Embedded DRAM (eDRAM) – DRAM arrays are also available as a process option for standard “logic”-type CMOS fabrication technologies – Ex: IBM 22 nm z Processor • “CP” Microprocessor chip on left: 8 cores, 64MB of eDRAM Level-3 cache, 678 mm2 die area, 4.0 billion transistors, 17 metal layers. eDRAM is used for Level-3 cache and memory controller; and also inside each processor for Level-2 and Branch Target Buffer caches. • “SC” System Controller chip on right: 480 MB of eDRAM Level-4 cache, 678 mm2 die area, 7.1 billion transistors, 15 metal layers • [Source: “22nm Next-Generation IBM System z Microprocessor”, ISSCC, 2015.] © B. Baas 266 DRAM • Read operation: BL – Wordline at Vdd – Bitline precharged to intermediate voltage Q level (e.g., Vdd/2) – Read bitline voltage is the “charge shared” result of storage capacitor and bitline capacitance WL • C_cell ~ C_bitline / (10-100) • ΔV_bitline ~ 250 mV • Read is a “destructive read” and value must be re-written to be read again • Circuit challenges: – More complex sense amplifiers – Many use differential sense amplifier with dummy cell – Higher noise susceptibility • Vdd not needed in array © B. Baas 267 Trench Capacitor • Deep trench capacitor provides high capacitance per area • Example to the right shows a DRAM cross section 268 © B. Baas http://www.ieee.org/portal/cms_docs_sscs/sscs/08Winter/sunami-fig3.jpg http://electron9.phys.utk.edu/phys136d/modules/m5/trench.gif Memory Array • Human hair on a 4 Mbit memory chip • Note DRAM trench capacitors 269 © B. Baas Source: Helmut Föll Memory Array • Red blood cells on a 1 Mbit memory chip 270 © B. Baas