Performance and Area Evaluations of Processor-based Benchmarks on FPGA Devices by Jiunn-Tyng, Kao A Doctoral Thesis submitted in partial fulfilment of the requirement for Master of Philosophy of Loughborough University January 2014 © Jiunn-Tyng, Kao, 2014 2 _________________________________________________ Abstract The computing system on SoCs is being long-term research since the FPGA technology has emerged due to its personality of re-programmable fabric, reconfigurable computing, and fast development time to market. During the last decade, uni-processor in a SoC is no longer to deal with the high growing market for complex applications such as Mobile Phones’ audio and video encoding, image and network processing. Due to the number of transistors on a silicon wafer is increasing, the recent FPGAs or embedded systems are advancing toward multi-processor-based design to meet tremendous performance and benefit this kind of systems are possible. Therefore, is an upcoming age of the MPSoC. In addition, most of the embedded processors are soft- cores, because they are flexible and reconfigurable for specific software functions and easy to build homogenous multi-processor systems for parallel programming. Moreover, behavioural synthesis tools are becoming a lot more powerful and enable to create datapath of logic units from high-level algorithms such as C to HDL and available for partitioning a HW/SW concurrent methodology. A range of embedded processors is able to implement on a FPGA-based prototyping to integrate the CPUs on a programmable device. This research is, firstly represent different types of computer architectures in modern embedded processors that are followed in different type of software applications (eg. Multi-threading Operations or Complex Functions) on FPGA-based SoCs; and secondly investigate their capability by executing a wide-range of multimedia software codes (Integer-algometric only) in different models of the processor- systems (uni-processor or multi-processor or Co-design), and finally compare those results in terms of the benchmarks and resource utilizations within FPGAs. All the examined programs were written in standard C and executed in a variety numbers of soft-core processors or hardware units to obtain the execution times. However, the number of processors and their customizable configuration or hardware datapath being generated are limited by a target FPGA resource, and designers need to understand the FPGA-based tradeoffs that have been considered - Speed versus Area. For this experimental purpose, I defined benchmarks into DLP / HLS catalogues, which are "data" and "function" intensive respectively. The programs of DLP will be executed in LEON3 MP and LE1 CMP multi- processor systems and the programs of HLS in the LegUp Co-design system on target FPGAs. In preliminary, the performance of the soft-core processors will be examined by executing all the benchmarks. The whole story of this thesis work centres on the issue of the execute times or the speed-up and area breakdown on FPGA devices in terms of different programs. Keywords: Soft-core, Multi-core, Co-design, Electronic-system-level, High-level-synthsis, Thread-level-parallelism, Data- level-parallelism, Symmetric-multi-processor, RISC, VLIW, LEON3 3 _________________________________________________ Acknowledgements This research was supported by the research group of Electronic Systems Design, School of Electronic and Electrical Engineering, Loughborough University, UK. I first would like to thank my supervisor and this research leader, Dr Vassilios Chouliaras. Secondly, I would like to thank my lab colleagues; David Stevens for the rearrange of Lempel-Ziv-Welch compression C code. He is a master of C programming language and Linux Ubuntu operating system and always opens for an answer; and Mark Milward for simulations of the LE1 CMP benchmarks. He is an expert in FPGA and SoC design. His help and advice have greatly helped my experimental analysis and philosophy. 4 _________________________________________________ TABLE OF CONTENTS Abstract……………….…………….…………………...…………..……......................................................…..2 Acknowledgments……………….…………….…………………...…………..…….......................................….3 Table of Contents……………….……….…………………...…………..……................................................….4 Table of Abbreviations……………….……….…………………...…………..…….......................................….8 List of Figures……………….……….…………………...…………..……....................................................…13 List of Tables……………….……….…………………...…………..……......................................................…16 1 Introduction……………….…………….…………………...…………..……......................................…17 1.1 Motivation……………………………………….………............…………………..........................……..17 1.2 Aims and Objectives of this Research….......................................................................................................18 1.3 Objectives of the Research and Goals….......................................................................................................19 1.4 Organization of the Thesis…........................................................................................................................22 2 Background Research and State of the Art ….........................................................................................24 2.1 Introduction………………………………………………………….......................……..............………..24 2.2 Types of Parallelism.………………………….........................................................................................…27 2.2.1 Instruction-Level-Parallelism (ILP)….....................................................................................................27 2.2.2 Data-Level-Parallelism (DLP)……………………………………………………............……………28 2.2.3 Thread-Level-Parallelism (TLP)……………………………………………....................…………….28 2.3 State-of-the-Art in Electronic-System-Level (ESL) Design ……………………………………………....29 2.3.1 Hardware/Software (HW/SW) Co-designs….........................................................................................30 2.4 FPGA Devices Overview……………………………………………………………………………..…....31 2.4.1 FPGA Fundamental Structures................................................................................................................31 2.4.2 Advanced FPGA Features……………………………………………………………………………...33 2.5 Embedded Processors on FPGAs……………………………………………………………..…................34 2.5.1 Hard and Soft Processors…....................................................................................................................36 2.5.2 Memory Architectures of the Multi-core Processor Systems….............................................................37 5 _________________________________________________ 2.6 Summary…………………………………………………………..……….....................................………38 3 Background of Methodologies and Implementations..................................................................………40 3.1 Introduction…...............................................................................................................................................40 3.2 Implementations of Data-Level-Parallelism (DLP)..........................................................…........................40 3.3 Implementations of High-Level-Synthesis (HLS)…………………………………..…..............................41 3.4 Design-Space-Exploration (DSE) on FPGA-Based......................................................................................44 3.4.1 Xilinx and Altera Resource Usage Conversion…...................................................................................44 3.4.2 DSE of Multi-core Processor System…..................................................................................................46 3.4.3 DSE of Co-design System.......................................................................................................................46 3.5 Summary…………………………………………………...........................................................................47 4 Evaluation in Single-core of Soft Embedded Processors….....................................................................48 4.1 Introduction…...............................................................................................................................................48 4.2 Background of LEON3, LE1, and Tiger-MIPS Processors…......................................................…………48 4.2.1 The LEON3 Processor…………………………………………....................................................…….49 4.2.2 The LE1 Processor……………………………………………………......................................………52 4.2.3 The Tiger-MIPS Processor…..................................................................................................................54 4.3 The Software (SW) Flow…..........................................................................................................................55 4.3.1 Experimental Implementations................................................................................................................55 4.4 Benchmark Collections….............................................................................................................................55 4.4.1 Data-intensive Programs……………………………………………........…………………………….56 4.4.2 Function-intensive Programs…...............................................................................................................56 4.4.3 Other Programs…....................................................................................................................................57